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this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s71ws-n_01 revision a amendment 4 issue date september 15, 2005 S71WS-NX0 based mcps stacked multi-chip product (mcp) 128/256/512 megabit (32m /16m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with psram type 4 data sheet advance information notice to readers: this document states the curre nt technical specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specific ations throughout the product life cycle, includ- ing development, qualification, initial producti on, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe- cific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. spansion llc therefore pl aces the following conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the pr oduct development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qua lification, initial production, and the subsequent phases in the manufacturing process that occur before full prod uction is achieved. changes to the technical specifications presented in a preliminary docume nt should be expected while keeping these as- pects of production under consideration. span sion places the following conditions upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of th is document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of pr oducts with different de signations (advance in- formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typica lly on the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designat ion is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the va lid combinations o ffered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s71ws-n_01 revision a amendment 4 issue date september 15, 2005 general description the s71ws-n series is a product line of stacked multi-chip product (mcp) packages and consists of the following items: ? one or more flash memory die ? psram type 4?compatible psram the products covered by this document are listed in the table below. for details about their spec- ifications, please refer to the individual constituent datasheet for further details. distinctive characteristics mcp features ? power supply voltage of 1.7 v to 1.95 v ? burst speed: 54 mhz, 66 mhz ? package ? 8 x 11.6 mm, 9 x 12 mm ? operating temperature ? wireless, ?25 c to +85 c S71WS-NX0 based mcps stacked multi-chip product (mcp) 128/256/512 megabit (32m /16m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with psram type 4 advance information device flash density psram density 512 mb 256 mb 128 mb 64 mb 128 mb 64 mb 32 mb 16 mb s71ws512nd0 ?? s71ws256nd0 ?? s71ws256nc0 ??? s71ws128nc0 ??
2S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information contents S71WS-NX0 based mcps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 special handling instructions for fbga packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 1.8 v ram type 4 ? based pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 look-ahead connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 tla084?84-ball fine-pitch ball grid array (fbga) 11.6 x 8.0 x 1.2 mm. . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.2 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . .18 5.3.3 fea084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . . 19 s29ws-n mirrorbit tm flash family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 input/output descriptions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.3 synchronous (burst) read mode & configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.3.4 continuous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.5 8-, 16-, 32-word linear burst read with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.6 8-, 16-, 32-word linear burst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.7 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.4 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.5 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5.1 single word programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5.2 write buffer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.5.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.5.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5.5 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.5.7 accelerated program/chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.5.8 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.5.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.7 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.8 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.9 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.10 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 advanced sector protection/unprotectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.6 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 3 advance information 11.6.2 acc method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.3 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.4 write pulse ?glitch protection? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.5 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 12.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.1 factory secured siliconsector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.3 secured silicon sector entry/exit command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.6 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.7 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.8.1 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.8.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.8.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.8.4 ac characteristics?asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.8.5 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.8.6 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.8.7 erase and programming performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.8.8 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 15.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 16 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 1.8v psram type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20 power up and standby mode timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 20.1 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 20.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 21 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 22 mode register setting operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 22.1 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 22.2 mode register setting timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 23 asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.1 asynchronous 4 page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.2 asynchronous write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.3 asynchronous write operation in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 24 synchronous burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 24.1 synchronous burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 24.2 synchronous burst write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 25 synchronous burst operation terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 25.1 clock (clk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 25.2 latency count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 25.3 burst length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 25.4 burst stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 25.5 wait control (wait#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 25.6 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 26 low power features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 26.7 partial array refresh (par) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.8 driver strength optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.1 internal tcsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 27 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 28 dc recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 29 capacitance (ta = 25c, f = 1 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16 30 dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 17 30.1 common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 31.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31.2 asynchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 31.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 31.3.1 asynchronous read timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 31.3.2 asynchronous write timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 31.3.3 asynchronous write timing waveform in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 31.3.4 asynchronous write timing waveform in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 32 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 32.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 32.2 synchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 32.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 32.3.1 synchronous burst operation timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 32.3.2 synchronous burst read timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 32.3.3 synchronous burst read stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 32.3.4 synchronous burst write stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 32.3.5 synchronous burst read suspend timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 33 transition timing waveform between read and write . . . . . . . . . . . . . . . . . . . . . . . . . . 139 1.8v psram type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 34 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 35 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 36 power up and standby mode timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 36.1 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 36.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 37 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 38 mode register setting operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0 38.1 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 38.2 mrs pin control type mode register setting timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 39 asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.1 asynchronous 4 page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.2 asynchronous write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.3 asynchronous write operation in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 40 synchronous burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 40.1 synchronous burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 40.2 synchronous burst write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 41 synchronous burst operation terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.1 clock (clk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.2 latency count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.3 burst length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.4 burst stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 41.5 wait control (wait#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 41.6 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 5 advance information 42 low power features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.1 internal tcsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.2 driver strength optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.3 partial array refresh (par) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 43 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 44 dc recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 45 capacitance (ta = 25c, f = 1 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 58 46 dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 46.1 common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47.2 asynchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 47.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 47.3.1 asynchronous read timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 47.3.2 asynchronous write timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 47.3.1 asynchronous write timing waveform in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 48 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 48.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 48.2 synchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 48.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 48.3.1 synchronous burst operation timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 48.3.2 synchronous burst read timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 48.3.3 synchronous burst read stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 48.3.4 synchronous burst write stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 48.3.5 synchronous burst read suspend timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 49 transition timing waveform between read and write . . . . . . . . . . . . . . . . . . . . . . . . . . 180 50 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information ta b l e s table 3.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9.1 s29ws256n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9.2 s29ws128n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10.2 address latency (s29ws256n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10.3 address latency (s29ws128n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10.4 address/boundary crossing latency (s29ws256n @ 80mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10.5 address/boundary crossing latency (s29ws256n @ 66 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10.6 address/boundary crossing latency (s29ws256n @ 54mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10.7 address/boundary crossing latency (s29ws128n). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10.8 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10.9 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10.10 autoselect addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10.11 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10.12 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10.13 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10.14 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10.15 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 10.16 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10.17 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10.18 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10.19 software functions and sample code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10.20 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10.21 reset lld function = lld_resetcmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 11.2 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 13.1 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 13.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 13.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 13.4 secured silicon sector exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 14.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 14.2 synchronous wait state requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 15.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 15.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 15.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 15.4 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 15.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 15.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 21.1 asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 05 table 21.2 synchronous burst read & asynchro nous write mode (a15/a14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 21.3 synchronous burst read & synchronous burst write mode (a15/a14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 1 06 table 22.1 mode register setting according to field of function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 22.2 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 22.3 mrs ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 25.1 latency count support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 25.2 number of clocks for 1st data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 25.3 burst sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 26.1 par mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 31.1 asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 31.2 asynchronous page read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 31.3 asynchronous write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 31.4 asynchronous write ac characteristics (ub# & lb# controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 7 advance information table 31.5 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 31.6 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 31.7 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 31.8 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 31.9 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 32.1 burst operation ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 32.2 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 32.3 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 32.4 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 32.5 burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 32.6 burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 32.7 burst read stop ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 32.8 burst write stop ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 32.9 burst read suspend ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 33.1 burst read to asynchronous write (address latch type) ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . 139 table 33.2 burst read to asynchronous write (low adv# type) ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 33.3 asynchronous write (address latch type) to burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . 141 table 33.4 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 33.5 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 33.6 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 37.1 asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 48 table 37.2 synchronous burst read & asynchro nous write mode (a15/a14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 37.3 synchronous burst read & synchronous burst write mode (a15/a14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 1 49 table 38.1 mode register setting according to field of function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 38.2 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 38.3 mrs ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 41.1 latency count support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 41.2 number of clocks for 1st data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 41.3 burst sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 42.1 par mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 47.1 asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 47.2 asynchronous page read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 47.3 asynchronous write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 47.4 asynchronous write ac characteristics (ub# & lb# controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 47.5 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 47.6 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 47.7 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 47.8 asynchronous write in synchronous mode ac characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 48.1 burst operation ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 48.2 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 48.3 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 48.4 burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 48.5 burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 48.6 burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 48.7 burst read stop ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 48.8 burst write stop ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 48.9 burst read suspend ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 49.1 burst read to asynchronous write (address latch type) ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . 180 table 49.2 burst read to asynchronous write (low adv# type) ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 49.3 asynchronous write (address latch type) to burst read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . 182 table 49.4 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 49.5 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 49.6 asynchronous write (low adv# type) to burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 185
8S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information figures figure 7.1 s29ws-n block diagram ................................................................................................ ....................22 figure 10.1 synchronous/asynchronous state diagram ................ .............................................................. .............27 figure 10.2 synchronous read .................................................................................................... ........................29 figure 10.3 single word program................................................................................................. ........................35 figure 10.4 write buffer programming operation .................................................................................. .................39 figure 10.5 sector erase operation .............................................................................................. ........................41 figure 10.6 write operation status flowch art .................................................................................... ....................48 figure 11.1 advanced sector protection/unp rotection ............................................................................. ................55 figure 11.2 ppb program/erase algorithm ......................................................................................... ....................58 figure 11.3 lock register program algori thm..................................................................................... ....................61 figure 14.1 maximum negative overshoot wave form ................................................................................. ............68 figure 14.2 maximum positive overshoot waveform ................. ................................................................ ..............68 figure 14.3 test setup .......................................................................................................... .............................69 figure 14.4 input waveforms and measuremen t levels .............................................................................. .............70 figure 14.5 v cc power-up diagram .............................................................................................................. ........70 figure 14.6 clk characterization ................................................................................................ .........................72 figure 14.7 clk synchronous burst mode read..................................................................................... .................74 figure 14.8 8-word linear burst with wrap around................................................................................ .................75 figure 14.9 8-word linear burst without wrap around ............. ................................................................ ...............75 figure 14.10 linear burst with rdy set one cycle before data .. .................................................................. ..............76 figure 14.11 asynchronous mode read............................................................................................. ......................77 figure 14.12 reset timings...................................................................................................... .............................78 figure 14.13 chip/sector erase operation timings ................................................................................ ...................80 figure 14.14 program oper ation timing using avd# ................................................................................ ................81 figure 14.15 program operation tim ing using clk in relationship to avd#......................................................... ........82 figure 14.16 accelerated unlock bypass prog ramming timing ....................................................................... ............83 figure 14.17 data# polling timings (during embedded algorithm) .. ................................................................ ...........83 figure 14.18 toggle bit timings (during embedded algorithm) .... ................................................................. .............84 figure 14.19 synchronous data polling timings/toggle bit timings ................................................................ ............84 figure 14.20 dq2 vs. dq6 ........................................................................................................ ............................85 figure 14.21 latency with boundary crossing when frequency > 66 mhz............................................................. .......85 figure 14.22 latency with boundary crossing into program/erase bank ............................................................. .........86 figure 14.23 example of wait states inse rtion ................................................................................... .....................87 figure 14.24 back-to-back read/write cycl e timings .............................................................................. .................88 figure 20.1 power up timing..................................................................................................... ........................ 104 figure 20.2 standby mode state machines ......................................................................................... ................. 104 figure 22.1 pin mrs timing waveform (oe# = v ih ) ............................................................................................. 108 figure 22.2 software mrs timing waveform ........................................................................................ ............... 109 figure 23.1 asynchronous 4-page read ............................................................................................ .................. 110 figure 23.2 asynchronous write.................................................................................................. ....................... 110 figure 24.1 synchronous burst read .............................................................................................. .................... 111 figure 24.2 synchronous burst write............................................................................................. ..................... 111 figure 25.1 latency configuration (read) ........................................................................................ .................... 112 figure 25.2 wait# and read/write latency control ................................................................................ ............. 113 figure 26.1 par mode execution and exit ......................................................................................... ................... 115 figure 31.1 par mode execution and exit ......................................................................................... ................... 117 figure 31.2 timing waveform of asynchronous read cycle .......................................................................... ......... 119 figure 31.3 timing waveform of page read cycle .................................................................................. .............. 120 figure 31.4 timing waveform of write cycle ........................ .............................................................. ................. 121 figure 31.5 timing waveform of write cycle(2) ................................................................................... ................ 122 figure 31.6 timing waveform of write cycl e (address latch type) ................................................................. ....... 123 figure 31.7 timing waveform of write cycle (low adv# type) ...................................................................... ....... 124 figure 31.8 timing waveform of write cycle (low adv# type) ...................................................................... ....... 125 figure 31.9 timing waveform of write cycle (low adv# type) ...................................................................... ....... 126
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 9 advance information figure 31.10 timing waveform of multiple write cycle (low adv# type)............................................................ ...... 127 figure 32.1 ac output load circuit.............................................................................................. ....................... 128 figure 32.2 timing waveform of basic burs t operation............................................................................ ............. 130 figure 32.3 timing waveform of burst read cycle (1) ............................................................................. ............. 131 figure 32.4 timing waveform of burst read cycle (2) ............................................................................. ............. 132 figure 32.5 timing waveform of burst read cycle (3) ............................................................................. ............. 133 figure 32.6 timing waveform of burst writ e cycle (1) ............................................................................ .............. 134 figure 32.7 timing waveform of burst writ e cycle (2) ............................................................................ .............. 135 figure 32.8 timing waveform of burst read stop by cs# ........................................................................... .......... 136 figure 32.9 timing waveform of burst write stop by cs# .......................................................................... ........... 137 figure 32.10 timing waveform of burst read suspend cycle (1).................................................................... .......... 138 figure 33.1 synchronous burst read to asyn chronous write (address latch type) ................................................... 139 figure 33.2 synchronous burst read to asyn chronous write (low adv# type) ........................................................ 140 figure 33.3 asynchronous write (address latch type) to synchronou s burst read timing ......................................... 141 figure 33.4 asynchronous write (low adv# type) to synchronous burst read timing .............................................. 142 figure 33.5 synchronous burst read to synchronous burst write timing............................................................ ..... 143 figure 33.6 synchronous burst write to synchronous burst read timing............................................................ ..... 144 figure 36.1 power up timing..................................................................................................... ........................ 147 figure 36.2 standby mode state machines ......................................................................................... ................. 147 figure 38.1 mode register setting timing (oe# = v ih ) ......................................................................................... 151 figure 39.1 asynchronous 4-page read ............................................................................................ .................. 152 figure 39.2 asynchronous write.................................................................................................. ....................... 152 figure 40.1 synchronous burst read .............................................................................................. .................... 153 figure 40.2 synchronous burst write............................................................................................. ..................... 153 figure 41.1 latency configuration (read) ........................................................................................ .................... 154 figure 41.2 wait# and read/write latency control ................................................................................ ............. 155 figure 42.1 par mode execution and exit ......................................................................................... ................... 157 figure 47.1 par mode execution and exit ......................................................................................... ................... 159 figure 47.2 timing waveform of asynchronous read cycle .......................................................................... ......... 161 figure 47.3 timing waveform of page read cycle .................................................................................. .............. 162 figure 47.4 timing waveform of write cycle ........................ .............................................................. ................. 163 figure 47.5 timing waveform of write cycle(2) ................................................................................... ................ 164 figure 47.6 timing waveform of write cycl e (address latch type) ................................................................. ....... 165 figure 47.7 timing waveform of write cycle (low adv# type) ...................................................................... ....... 166 figure 47.8 timing waveform of write cycle (low adv# type) ...................................................................... ....... 167 figure 47.9 timing waveform of mu ltiple write cycle (low adv# type)............................................................. ..... 168 figure 48.1 ac output load circuit.............................................................................................. ....................... 169 figure 48.2 timing waveform of basic burs t operation............................................................................ ............. 171 figure 48.3 timing waveform of burst read cycle (1) ............................................................................. ............. 172 figure 48.4 timing waveform of burst read cycle (2) ............................................................................. ............. 173 figure 48.5 timing waveform of burst read cycle (3) ............................................................................. ............. 174 figure 48.6 timing waveform of burst writ e cycle (1) ............................................................................ .............. 175 figure 48.7 timing waveform of burst writ e cycle (2) ............................................................................ .............. 176 figure 48.8 timing waveform of burst read stop by cs# ........................................................................... .......... 177 figure 48.9 timing waveform of burst write stop by cs# .......................................................................... ........... 178 figure 48.10 timing waveform of burst read suspend cycle (1).................................................................... .......... 179 figure 49.1 synchronous burst read to asyn chronous write (address latch type) ................................................... 180 figure 49.2 synchronous burst read to asyn chronous write (low adv# type) ........................................................ 181 figure 49.3 asynchronous write (address latch type) to synchronou s burst read timing ......................................... 182 figure 49.4 asynchronous write (low adv# type) to synchronous burst read timing .............................................. 183 figure 49.5 synchronous burst read to synchronous burst write timing............................................................ ..... 184 figure 49.6 synchronous burst write to synchronous burst read timing............................................................ ..... 185
10 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 1 product selector guide note: 0 (protected), 1 (unprotected [default state]) device model numbers flash psram density (mb) flash speed (mhz) psram speed (mhz) dyb power-up state ( see note ) psram supplier package (mm) s71ws256nc0 a3 ws256n 64 54 54 0 1.8v ram type 4 11.6x8.0x1.2 a7 1 a2 66 66 0 a6 1 s71ws256nd0 y3 128 54 54 0 9x12x1.2 y7 1 y2 66 66 0 y6 1 s71ws512nd0 e3 ws512n 128 54 54 0 9x12x1.4 e7 1 e2 66 66 0 e6 1 s71ws128nc0 a3 ws128n 64 54 54 0 11.6x8.0x1.2 a7 1 a2 66 66 0 a6 1
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 11 advance information 2 ordering information the ordering part number is formed by a valid combination of the following: package marking note: the package marking omits the leading s from the ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s71ws 256 n c 0 ba w a 3 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel ram supplier, dyb power up, speed combinations 3 = ram type 4, 0, 54 mhz 7 = ram type 4, 1, 54 mhz 2 = ram type 4, 0, 66 mhz 6 = ram type 4, 1, 66 mhz package modifier a = 1.2 mm, 8 x 11.6, 84-ball fbga e = 1.2 mm, 9 x 12, 84-ball fbga y = 1.4 mm, 9 x 12, 84-ball fbga temperature range w = wireless (-25 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package chip contents?2 no content psram density c = 64 mb d = 128 mb process technology n = 110nm mirrorbit? technology flash density 512 = 512mb (2x256mb) 256 = 256mb device family s71ws= multi-chip product 1.8 volt-only simultaneous read/write burst mode flash memory + xram valid combinations s71ws128n c 0ba, bf w a 2, 6, 3, 7 s71ws256n de3, 7 c a 2, 6, 3, 7 s71ws512n d y2, 6 e 2, 6, 3, 7
12 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 3 input/output descriptions table 3.1 identifies the input and output package connections provided on the device. table 3.1 input/output descriptions symbol description a23-a0 address inputs dq15-dq0 data input/output oe# output enable input. asynchronous relative to clk for the burst mode. we# write enable input. v ss ground nc no connect; not connected internally rdy ready output. indicates the status of the burst read. the wait# pin of the psram is tied to rdy. clk clock input. in burst mode, after th e initial word is output, subseque nt active edges of clk increment the internal address counter. should be at v il or v ih while in as ynchronous mode avd# address valid input. indicates to device that th e valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs f-rst# hardware reset input. low = device resets and returns to reading array data f-wp# hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc accelerated input. at v hh , accelerates programming; automatica lly places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce1# chip-enable input for psram. f1-ce# chip-enable input for flash 1. asynchronous relative to clk for burst mode. f2-ce# chip-enable input for flash 2. asynchronous relative to clk for burst mode. th is applies to the 512mb mcp only. r-mrs mode register select for type 4. f-vcc flash 1.8 volt-only single power supply. r-vcc psram power supply. r-ub# upper byte control (psram). r-lb# lower byte control (psram) dnu do not use
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 13 advance information 4 mcp block diagram notes: 1. for 1 flash + psram, f1-ce# = ce#. for 2 flash + psram, ce# = f1-ce# and f2-ce# is the chip-enable pin for the second flash. 2. only needed for s71ws512n. 3. for the 128m psram devices, there are 23 shared addresses. v id v cc rdy psram flash 1 dq15 to dq0 flash-only address shared address f1-ce# acc r-ub# r-ce2 r-vcc v cc v ccq f-vcc 22 clk clk wp# oe# we# f-rst# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 r-ce1# ce# we# oe# ub# r-lb# lb# 22 f2-ce# clk avd# flash 2 wait# ce2 ( note 1 ) ( note 1 ) ( note 3 )
14 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 5 connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the s71ws-n. 5.1 special handling instru ctions for fbga packages special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning meth- ods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 15 advance information 5.2 connection diagrams 5.2.1 1.8 v ram type 4 ? based pinout notes: 1. in mcps based on a single s29ws256n (s71ws256n), ball b5 is rfu. in mcps based on two s29ws256n (s71ws512), ball b5 is or f2-ce#. 2. addresses are shared between flash and ram depending on the density of the psram. mcp flash-only addresses shared addresses s71ws128nc0 a22 a21-a0 s71ws256nc0 a23-a22 a21-a0 s71ws512nd0 a23 a22-a0 a7 a3 a2 dq8 dq14 r-ce1# r-lb# f-acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 rdy a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 r-mrs h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-v cc r-v cc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu clk f2-ce# rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-v cc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 avd# rfu rfu rfu rfu f-wp# rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu ram only shared flash xip only legend reserved for future use 2nd flash only 1st flash only 84-ball fine-pitch ball grid array type 4-based pinout (top view, balls facing down)
16 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 5.2.2 look-ahead connection diagram notes: ball 3.0 v v cc 1.8 v v cc 1. in a 3.0v system, the gl device used as data has to have wp tied to v cc 2. f1 and f2 denote xip/flash, f3 and f4 denote data/companion flash d2 nc f-wp# d5 wp#/acc acc f5 ry/by f-rdy/r-wait# legend: xram shared psram only flash/xram shared flash/data shared rfu (reserved for future use) code flash only x mirrorbit data only x x x x x x x x x x x x x x rfu b1 b10 rfu b2 rfu b9 rfu f-dqs0 n1 n1 f-dqs1 n10 rfu n2 rfu n9 rfu p1 rfu p10 p2 rfu rfu p9 a1 rfu rfu a10 rfu a2 rfu a9 d3 a7 acc d5 r-lb# d4 d7 a8 wp# d2 d8 a11 f3-ce# d9 d6 we# f3 f3 a5 f5 rdy/wait# f4 f4 a18 f7 f7 a9 f2 f2 a2 f8 f8 a13 f9 f9 a21 f6 f6 a20 j3 oe# j5 dq3 j4 dq9 j7 dq13 f1-ce# j2 j8 dq15 r-cre or r-mrs j9 j6 dq4 l3 l3 dq8 l5 l5 dq11 l4 l4 dq2 l7 l7 dq5 r-vcc l2 l8 l8 dq14 wp# l9 l6 l6 a25 c3 vss f2-ce# c5 c4 clk f-clk# c7 avd# c2 r-oe# c8 f2-oe# c9 f-vcc c6 c6 c 6 c 6 e3 a6 f-rst# c7 r-ub# d4 e7 a19 e2 a3 e8 a12 e9 a15 r1-ce2 e6 a4 g3 g3 r2-ce1 g5 a17 g4 g4 a10 g7 g7 a1 g2 g2 a14 g8 g8 a22 g9 g9 a23 g6 g6 h3 h3 vss r2-vcc h5 h4 h4 dq1 h7 dq6 h2 h2 a0 h8 a24 h9 a16 r2-ce2 h6 dq0 k3 k3 f-vcc k5 dq10 k4 k4 k7 k7 dq12 r1-ce1# k2 dq7 k8 k8 k9 k9 vss r1-vcc e6 m3 a26 f-vcc m5 m4 vss r-vccq m7 m2 a27 f-vccq m8 r-clk# m9 f4-ce# m6
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 17 advance information 5.3 physical dimensions 5.3.1 tla084?84-ball fine-pitch ball grid array (fbga) 11.6 x 8.0 x 1.2 mm 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
18 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 5.3.2 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.2 mm 3426\ 16-038.2 2 package tsd 084 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.94 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 m c mc ab 0.08 pin a1 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 19 advance information 5.3.3 fea084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.4 mm bsc is an ansi standard for basic space centering 3423 \ 16-038.21 a package fea 084 jedec n/a d x e 12.00 mm x 9.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.11 --- 1.26 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 0.15 c a b m c m 0.08
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s71ws-n_01 revision a amendment 4 issue date september 15, 2005 general description the spansion s29ws256/128 are mirrorbit tm flash products fabricated on 110-nm process technology. these burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate da ta and address pins. these products can operate up to 80 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for today?s demanding wireless applications requiring higher density, better performance and lowered power consumption. distinctive characteristics ? single 1.8 v read/program/erase (1.70?1.95 v) ? 110 nm mirrorbit? technology ? simultaneous read/write operation with zero latency ? 32-word write buffer ? sixteen-bank architecture consisting of 16/8 mwords for ws256n/128n, respectively ? four 16 kword sectors at both top and bottom of memory array ? 254/126 64 kword sectors (ws256n/128n) ? programmable linear (8/16/32) with or without wrap around and continuous burst read modes ? secured silicon sector region consisting of 128 words each for factory and customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec (42.4) standard ? hardware (wp#) protection of top and bottom sectors ? dual boot sector config uration (top and bottom) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst control register settings ? acc input pin to reduce factory programming time ? support for common flash interface (cfi) performance characteristics s29ws-n mirrorbit tm flash family s29ws256n, s29ws128n 256/128 megabit (16/8 m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory advance information read access times speed option (mhz) 80 66 54 max. synch. latency, ns (t iacc ) 80 80 80 max. synch. burst access, ns (t bacc ) 9 11.2 13.5 max. asynch. access time, ns (t acc ) 80 80 80 max ce# access time, ns (t ce ) 80 80 80 max oe# access time, ns (t oe ) 13.5 13.5 13.5 current consumption (typical values) continuous burst read @ 80 mhz 38 ma simultaneous operation (asynchronous) 50 ma program (asynchronous) 19 ma erase (asynchronous) 19 ma standby mode (asynchronous) 20 a typical program & erase times single word programming 40 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v acc ) per word 6 s sector erase (16 kword sector) 150 ms sector erase (64 kword sector) 600 ms
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 21 advance information 6 input/output descri ptions & logic symbol table 6.1 identifies the input and output package connections provided on the device. table 6.1 input/output descriptions symbol ty p e description a23?a0 input address lines for ws256n (a22-a0 for ws128). dq15?dq0 i/o data input/output. ce# input chip enable. asynchrono us relative to clk. oe# input output enable. asynchronous relative to clk. we# input write enable. v cc supply device power supply. v ss i/o ground. nc no connect not connected internally. rdy output ready. indicates when valid burs t data is ready to be read. clk input clock input. in burst mode, after the initial wo rd is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode. avd# input address valid. indicates to device that the valid address is present on the address inputs. when low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be la tched at the next active clock edge. when high, device ignores address inputs. reset# input hardware reset. low = device resets and returns to reading array data. wp# input write protect. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. acc input acceleration input. at v hh , accelerates programming; auto matically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. rfu reserved reserved for future use (see mcp l ook-ahead pinout for use with mcp).
22 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 7 block diagram figure 7.1 s29ws-n block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a max ?a0* rdy buffer rdy burst state control burst address counter avd# clk * ws256n: a23-a0 ws128n: a22-a0
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 23 advance information 8 additional resources visit www.amd.com and www.fujitsu.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? understanding burst mode flash memory devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad technical support contact your local sales office or contact spansion llc directly for additional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujitsu.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion llc locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
24 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 9 product overview the s29ws-n family consists of 256, 128 mbit, 1.8 volts-only, simultaneous read/write burst mode flash device optimized for today?s wireless designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 16 or 8 mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. these products also offe r single word programming or a 32-word buffer for programming with program/erase and suspend function ality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon area for storing customer and factory secu red information. the secured silicon sector is one time programmable. 9.1 memory map the s29ws256/128n mbit devices consist of 16 banks organized as shown in ta b l e 9 . 1 ? ta b l e 9 . 2 . note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not explicitly liste d (such as sa005?sa017) have sector starting and ending addresses that form the sam e pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 9.1 s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 2 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 15 128 sa004 to sa018 010000h?01ffffh to 0f0000h?0fffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 2 mb 16 128 1 sa019 to sa034 100000h?10ffffh to 1f0000h?1fffffh 2 mb 16 128 2 sa035 to sa050 200000h?20ffffh to 2f0000h?2fffffh 2 mb 16 128 3 sa051 to sa066 300000h?30ffffh to 3f0000h?3fffffh 2 mb 16 128 4 sa067 to sa082 400000h?40ffffh to 4f0000h?4fffffh 2 mb 16 128 5 sa083 to sa098 500000h?50ffffh to 5f0000h?5fffffh 2 mb 16 128 6 sa099 to sa114 600000h?60ffffh to 6f0000h?6fffffh 2 mb 16 128 7 sa115 to sa130 700000h?70ffffh to 7f0000h?7fffffh 2 mb 16 128 8 sa131 to sa146 800000h?80ffffh to 8f0000h?8fffffh 2 mb 16 128 9 sa147 to sa162 900000h?90ffffh to 9f0000h?9fffffh 2 mb 16 128 10 sa163 to sa178 a00000h?a0ffffh to af0000h?afffffh 2 mb 16 128 11 sa179 to sa194 b00000h?b0ffffh to bf0000h?bfffffh 2 mb 16 128 12 sa195 to sa210 c00000h?c0ffffh to cf0000h?cfffffh 2 mb 16 128 13 sa211 to sa226 d00000h?d0ffffh to df0000h?dfffffh 2 mb 16 128 14 sa227 to sa242 e00000h?e0ffffh to ef0000h?efffffh 2 mb 15 128 15 sa243 to sa257 f00000h?f0ffffh to fe0000h?feffffh 4 32 sa258 ff0000h?ff3fffh contains four smaller sectors at top of addressable memory. sa259 ff4000h?ff7fffh sa260 ff8000h?ffbfffh sa261 ffc000h?ffffffh
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 25 advance information note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not explicitly liste d (such as sa005?sa009) have sector starting and ending addresses that form the sam e pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 9.2 s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 1 mb 4 32 0 sa000 00000 0h?003fffh contains four smaller sectors at bottom of addressable memory. 32 sa001 00400 0h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 7 128 sa004 to sa010 010000h ?01ffffh to 070000h?07ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 1 mb 8 128 1 sa011 to sa01 8 080000h?08ffffh to 0f0000h?0fffffh 1 mb 8 128 2 sa019 to sa02 6 100000h?10ffffh to 170000h?17ffffh 1 mb 8 128 3 sa027 to sa03 4 180000h?18ffffh to 1f0000h?1fffffh 1 mb 8 128 4 sa035 to sa04 2 200000h?20ffffh to 270000h?27ffffh 1 mb 8 128 5 sa043 to sa05 0 280000h?28ffffh to 2f0000h?2fffffh 1 mb 8 128 6 sa051 to sa05 8 300000h?30ffffh to 370000h?37ffffh 1 mb 8 128 7 sa059 to sa06 6 380000h?38ffffh to 3f0000h?3fffffh 1 mb 8 128 8 sa067 to sa07 4 400000h?40ffffh to 470000h?47ffffh 1 mb 8 128 9 sa075 to sa08 2 480000h?48ffffh to 4f0000h?4fffffh 1 mb 8 128 10 sa083 to sa 090 500000h?50ffffh to 570000h?57ffffh 1 mb 8 128 11 sa091 to sa 098 580000h?58ffffh to 5f0000h?5fffffh 1 mb 8 128 12 sa099 to sa 106 600000h?60ffffh to 670000h?67ffffh 1 mb 8 128 13 sa107 to sa 114 680000h?68ffffh to 6f0000h?6fffffh 1 mb 8 128 14 sa115 to sa 122 700000h?70ffffh to 770000h?77ffffh 1 mb 7 128 15 sa123 to sa129 780000h?78ffffh to 7e0000h?7effffh 4 32 sa130 7f0000h?7f3fffh contains four smaller sectors at top of addressable memory. 32 sa131 7f4000h?7f7fffh 32 sa132 7f8000h?7fbfffh 32 sa133 7fc000h?7fffffh
26 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10 device operations this section describes the read, program, erase, simultaneous read/write operations, handshak- ing, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see tables 15.1 and 15.2 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the sys- tem must write the reset command to return the device to the reading array data mode. 10.1 device operation table the device must be setup appropriately for each operation. ta b l e 1 0 . 1 describes the required state of each control pin for any particular operation. table 10.1 device operations legend: l = logic 0, h = logic 1, x = don?t care, i/o = input/output. 10.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asyn- chronously with the address on its inputs. the device defaults to reading array data asynch ronously after device po wer-up or ha rdware re- set. to read data from the memory array, the system must first assert a valid address on a max ? a0, while driving avd# and ce# to v il . we# must remain at v ih . the rising edge of avd# latches the address. the oe# signal must be driven to v il , once avd# has been driven to v ih . data is output on a/dq15-a/dq0 pins after the access time (t oe ) has elapsed from the falling edge of oe#. operation ce# oe# we# addresses dq15?0 reset# clk avd# asynchronous read - addresses latched l l h addr in data out h x asynchronous read - addresses steady state l l h addr in data out h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations (synchronous) load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus ll h x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle lx haddr in i/o h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 27 advance information 10.3 synchronous (burst) read mode & configuration register when a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. after an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. the device offers both continuous and linear me thods of burst read op eration, which are dis- cussed in subsections 10.3.4 and 10.3.5 , and 10.3.6 . since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable th e burst read mode. other configuration register settings include the number of wait states to insert before the initial word (t iacc ) of each burst access, the burst mode in which to operate, and when rdy indicates data is ready to be read. prior to entering the burst mode, the system shou ld first determine the configuration register set- tings (and read the current register settings if desired via the read configuration register command sequence), and then write the configuration register command sequence. see section 10.3.7 , configuration register , and ta b l e 1 5 . 1 , memory array commands for further details. figure 10.1 synchronous/asynchronous state diagram the device outputs the initial word subject to the following operational conditions: ? t iacc specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. ? configuration register setting cr13?cr11: th e total number of clock cycles (wait states) that occur before valid data appears on th e device outputs. the effect is that t iacc is lengthened. the device outputs subsequent words t bacc after the active edge of each successive clock cycle, which also increments the internal address counter. the device outputs burst data at this rate sub- ject to the following operational conditions: power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1)
28 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information ? starting address: whether the address is divisibl e by four (where a[1:0] is 00). a divisible- by-four address incurs the least number of additi onal wait states that occur after the initial word. the number of additional wait states requ ired increases for burst operations in which the starting address is one, two, or three loca tions above the divisible-by-four address (i.e., where a[1:0] is 01, 10, or 11). ? boundary crossing: there is a boundary at every 128 words due to the internal architecture of the device. one additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock fr equency. please refer to the tables below. ? clock frequency: the speed at which the device is expected to burst data. higher speeds require additional wait states after the initial word for proper operation. in all cases, with or without latency, the rdy output indicates when the next data is available to be read. ta b l e s 10.2 - 10.7 reflect wait states required for s29ws256/128n devices. refer to the ?config- uration register? table (cr11 - cr14) and timing diagrams for more details. ta b l e 1 0 . 2 address latency (s29ws256n) ta b l e 1 0 . 3 address latency (s29ws128n) ta b l e 1 0 . 4 address/boundary crossing latency (s29ws256n @ 80mhz) ta b l e 1 0 . 5 address/boundary crossing latency (s29ws256n @ 66 mhz) word wait states cycle 0 x ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 x ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 x ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 x ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5, 6, 7 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5, 6, 7 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 7 ws d0 d1 d2 d3 1 ws 1 ws d4 d5 d6 1 7 ws d1 d2 d3 1 ws 1 ws 1 ws d4 d5 d6 2 7 ws d2 d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 3 7 ws d3 1 ws 1 ws 1 ws 1 ws 1 ws d4 d5 d6 word wait states cycle 0 6 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 6 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 6 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 6 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 29 advance information ta b l e 1 0 . 6 address/boundary crossing latency (s29ws256n @ 54mhz) ta b l e 1 0 . 7 address/boundary crossing latency (s29ws128n) figure 10.2 synchronous read word wait states cycle 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 5, 6, 7 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 5, 6, 7 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7 write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 note: setup configuration register parameters no refer to the latency tables.
30 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10.3.4 continuous burst read mode in the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. the burst read mode continue s until the system drives ce# high, or reset= v il . continuous burst mode can al so be aborted by asserting avd# low and providing a new ad- dress to the device. if the address being read crosses a 128-word line boundary (as mentioned above) and the sub- sequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table ( ta b l e 1 0 . 9 ). if the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. upon completion of status read or program or erase operation, the host ca n restart a burst read operation using a new ad- dress and avd# pulse. 10.3.5 8-, 16-, 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con- secutive addresses that are determined by the group within which the starting address falls. the groups are sized according to the number of word s read in a single burst sequence for a given mode (see ta b l e 1 0 . 8 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3fh, and the burst sequence would be 3c-3d-3e-3f-38-39-3a-3bh. thus, the device outputs all words in that burst address group until all word are read, regardless of where the start- ing address occurs in the address group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word li near wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. ta b l e 1 0 . 8 burst address groups 10.3.6 8-, 16-, 32-word linear burst without wrap around if wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory addres s of the selected number of words. the burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. for example, if the starting address in the 8- word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3c-3d-3e-3f-40-41-42-43h if wrap around is not enabled. the next address to be read re quires a new address and avd# pulse. note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state. mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 31 advance information 10.3.7 configuration register the configuration register sets various operational parameters associated with burst mode. upon power-up or hardware re set, the device defaults to the asynchronous read mode, and the config- uration register settings are in their default state. the host system should determine the proper settings for the entire configuration register, and then execute the set configuration register command sequence, before attempting burst operat ions. the configuration register is not reset after deasserting ce#. the configuration register can also be read using a command sequence (see ta b l e 1 5 . 1 ). the following list describes the register settings. ta b l e 1 0 . 9 configuration register reading the configuration table. the configuration register can be read with a four-cycle com- mand sequence. see table 15.1 for sequence details. once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. cr bit function settings (binary) cr15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous read mode (default) enabled cr14 reserved 1 = s29ws256n at 6 or 7 wait state setting 0 = all others 54 mhz 66 mhz 80 mhz cr13 programmable wait state s29ws128n 011 011 = data valid on 5th active clk edge after addresses latched 100 = data valid on 6th active clk edge after addresses latched 101 = data valid on 7th active clk edge after addresses latched (default) 110 = reserved 111 = reserved inserts wait states before initial data is available. setting greater number of wait states before initial data reduces latency after initial data. (notes 1 , 2 ) s29ws256n cr12 s29ws128n 100 s29ws256n cr11 s29ws128n 101 s29ws256n cr10 rdy polarity 0 = rdy signal active low 1 = rdy signal active high (default) cr9 reserved 1 = default cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) when cr13-cr11 are set to 000, rdy is active with data regardless of cr8 setting. cr7 reserved 1 = default cr6 reserved 1 = default cr5 reserved 0 = default cr4 reserved 0 = default cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 cr1 cr0 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) notes: 1. refer to tables 10.2 - 10.7 for wait states requirements. 2. refer to synchronous burst read timing diagrams 3. configuration register is in the default state upon power-up or hardware reset.
32 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10.4 autoselect the autoselect is used for manufacturer id, device identification, and sector protection informa- tion. this mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. the autoselect codes can also be accessed in-sys- tem. when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 1 0 . 1 0 ). the remaining address bits are don't care. the most signif- icant four bits of the address during the thir d write cycle selects the bank from which the autoselect codes are read by the host. all other banks can be accessed normally for data read without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. autoselect does not support si multaneous operations or burst mode. ? the system must write the reset command to re turn to the read mode (or erase-suspend- read mode if the bank was previously in erase suspend). see ta b l e 1 5 . 1 for command sequence details. ta b l e 1 0 . 1 0 autoselect addresses description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2230 (ws256n) 2231 (ws128n) device id, word 3 (ba) + 0fh 2200 indicator bits ( see note ) (ba) + 03h dq15 - dq8 = reserved dq7 (factory lock bit): 1 = locked, 0 = not locked dq6 (customer lock bit): 1 = locked, 0 = not locked dq5 (handshake bit): 1 = reserved, 0 = standard handshake dq4, dq3 (wp# protection boot code): 00 = wp# protects both top boot and bottom boot sectors. 01, 10, 11 = reserved dq2 = reserved dq1 (dyb power up state [lock register dq4]): 1 = unlocked (user option), 0 = locked (default) dq0 (ppb eraseability [lock register dq3]): 1 = erase allowed, 0 = erase disabled sector block lock/ unlock (sa) + 02h 0001h = locked, 0000h = unlocked note: for ws128n and ws064, dq1 and dq0 are reserved. ta b l e 1 0 . 1 1 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write baxaaah bax555h 0x00aah unlock cycle 2 write bax555h bax2aah 0x0055h autoselect command write baxaaah bax555h 0x0090h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 33 advance information notes: 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manufac- turer id. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on sp ansion flash memory software development guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ ta b l e 1 0 . 1 2 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxh base + xxxh 0x00f0h
34 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10.5 program/erase operations these devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. ho wever, prior to any programming and or erase op- eration, devices must be setup appropriately as outlined in the configuration register ( table 10.8 ). for any program and or erase operations, including writing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is complete, the device returns to the read mode. ? the system can determine the status of the prog ram operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. ? a ?0? cannot be programmed back to a ?1.? attempting to do so causes the device to set dq5 = 1 (halting any further operation and requir ing a reset command). a succeeding read shows that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi fu nctions are unavailable when a program oper- ation is in progress. ? a hardware reset immediately terminates th e program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word pro- gramming operation. 10.5.1 single word programming single word programming mode is the simplest method of prog ramming. in this mode, four flash command write cycles are used to program an in dividual flash address. the data for this pro- gramming operation could be 8-, 16- or 32-bits wide. while this method is supported by all spansion devices, in general it is not recomm ended for devices that support write buffer pro- gramming. see ta b l e 1 5 . 1 for the required bus cycles and figure 10.3 for the flowchart. when the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper- ation by using dq7 or dq6. refer to the write op eration status section for information on these status bits. ? during programming, any command (except th e suspend program command) is ignored. ? the secured silicon sector, autoselect, and cf i functions are unavailable when a program op- eration is in progress.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 35 advance information ? a hardware reset immediately terminates the program operation. the program command se- quence should be reinitiated once the device ha s returned to the read mode, to ensure data integrity. figure 10.3 single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
36 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information note: base = base address. the following is a c source code example of us ing the single word prog ram function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 10.5.2 write buffer programming write buffer programming allows the system to write a maximum of 32 words in one program- ming operation. this results in a faster effective word programming time than the standard ?word? programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming occurs. at this point, the sys- tem writes the number of ?word locations minus 1? that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how many write buffer ad- dresses are loaded with data and therefore when to expect the ?program buffer to flash? confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the ?write-buffer-page? address. all subsequent address/data pairs must fall with in the elected-write-buffer-page. the ?write-buffer-page? is selected by using the addresses a max - a5. the ?write-buffer-page? addresses must be the sa me for all address/data pairs loaded into the write buffer. (this means write buffer programmin g cannot be performed across multiple ?write- buffer-pages.? this also means that write buffe r programming cannot be performed across mul- tiple sectors. if the system attempts to load programming data outside of the selected ?write- buffer-page?, the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address location is loaded multiple times, the ?address/data pair? counter is decremented for every data load operation. also, the last data loaded at a location be- fore the ?program buffer to flash? confirm comm and is programmed into the device. it is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer- address location. once the specified number of write buffer locations have been loaded, the sys- tem must then write the ?program buffer to flash? command at the sector address. any other ta b l e 1 0 . 1 3 software functions and sample code cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 37 advance information address/data write combinations abort the write buffer programming operation. the device goes ?busy.? the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the devi ce status during wr ite buffer programming. the write-buffer ?embedded? programming operat ion can be suspended using the standard sus- pend/resume commands. upon successful completion of the write buffer programming operation, the device returns to read mode. the write buffer programming sequence is abor ted under any of the following conditions: ? load a value that is greater than the page buff er size during the ?number of locations to pro- gram? step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different wr ite-buffer-page than the one selected by the ?starting address? during the ?write buffe r data loading? stage of the operation. ? write data other than the ?confirm command? after the specified number of ?data load? cy- cles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last address location loaded?), dq6 = toggle, dq5 = 0. this indicate s that the write buffer programming operation was aborted. a ?write-to-buffer-abort reset? command sequence is required when using the write buffer programming features in unlock bypass mode. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of hand ling multiple write buffer progra mming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. write buffer programming is approximately eight times faster than programming one word at a time.
38 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible. the following is a c source code example of us ing the write buffer program function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ ta b l e 1 0 . 1 4 software functions and sample code cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 39 advance information figure 10.4 write buffer programming operation 10.5.3 sector erase the sector erase function erases one or more sectors in the memory array. (see table 15.1 , memory array commands ; and figure 10.5 , sector erase operation .) the device does not re- quire the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful sector erase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa = 0x29h wait 4 s (recommended) perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
40 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information after the command sequence is written, a sector erase time-out of no less than t sea occurs. dur- ing the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see the dq3: sector erase timeout state indicator section.) the time-out begins from the rising edge of the fi nal we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and ad- dresses are no longer la tched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to write operation status for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a ha rdware reset immediately terminates the erase operation. if that occurs, the sector erase comm and sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 10.5 illustrates the algorithm for the erase operation. refer to the erase and programming performance section for parameters and timing diagrams. the following is a c source code example of using the sector erase function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ ta b l e 1 0 . 1 5 software functions and sample code cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea .
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 41 advance information figure 10.5 sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s (recommended) perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? each additional cycle must be written within t sea timeout timeout resets after each additional cycle is written the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands no limit on number of sectors commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data notes: 1. see table 15.1 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. (see figure 10.6)
42 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10.5.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by ta b l e 1 5 . 1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprogram s and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to pr ovide any controls or timings during these oper- ations. the ?command definition? section in the appendix shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to ?write operatio n status? for information on these status bits. any commands written during the chip erase oper ation are ignored. however, note that a hard- ware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the following is a c source code example of using the chip erase function. refer to the span- sion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash me mory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ 10.5.5 erase suspend/erase resume commands when the erase suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and su spends the erase operation. the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the min- imum t sea time-out period during the sector erase command sequence. the erase suspend command is ignored if written du ring the chip erase operation. when the erase suspend command is written after the t sea time-out period has expired and dur- ing the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. additionaly, when an erase suspend command is written during an active erase operation, status information is un available during the transition from the sector erase operation to the erase suspended state. ta b l e 1 0 . 1 6 software functions and sample code cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 43 advance information after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de- vice ?erase suspends? all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to table 10.20 for information on these status bits. after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system ca n also issue the autoselect command sequence. refer to the ?write buffer programming operat ion? section and the ?autoselect command se- quence? section for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing. the following is a c source code example of using the erase suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the erase resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 10.5.6 program suspend/pr ogram resume commands the program suspend command allows the system to interrupt an embedded programming op- eration or a ?write to buffer? programming operation so that data can read from any non- suspended sector. when the program suspend command is written during a programming pro- cess, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are ?don't -cares? when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a program- ming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a re ad is needed from the secured silicon sector area, then user must use the proper command sequences to enter and exit this region. ta b l e 1 0 . 1 7 software functions and sample code cycle operation byte address word address data 1 write bank address bank address 00b0h cycle operation byte address word address data 1 write bank address bank address 0030h
44 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information the system may also write the autoselect command sequence when the device is in program sus- pend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the de vice exits the autoselect mode, the device re- verts to program suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system must write the program resume command (address bits are ?don't care?) to exit the program suspend mode and continue the programm ing operation. further writes of the program resume command are ignored. another program suspend command can be written after the de- vice has resumed programming. the following is a c source code example of us ing the program suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the program resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 10.5.7 accelerated program/chip erase accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the acc function. th is method is faster than the standard chip program and erase command sequences. the accelerated chip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program and erase should be performed at room tem- perature (25 c 10 c). if the system asserts v hh on this input, the device automatically enters the aforementioned un- lock bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. the system can then use the write buffer load command se- quence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded pro- gram or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising acc to v hh . ? the acc pin must not be at v hh for operations other than accelerated programming and ac- celerated chip erase, or device damage may result. ta b l e 1 0 . 1 8 software functions and sample code cycle operation byte address word address data 1 write bank address bank address 00b0h cycle operation byte address word address data 1 write bank address bank address 0030h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 45 advance information ? the acc pin must not be left floating or unconne cted; inconsistent behavior of the device may result. ? acc locks all sector if set to v il ; acc should be set to v ih for all other conditions. 10.5.8 unlock bypass the device features an unlock bypass mode to facilitate faster word pr ogramming. once the de- vice enters the unlock bypass mode, only two write cycles are required to program data, instead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. the ?command de finition summary? sec- tion shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the following are c source code examples of us ing the unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. ta b l e 1 0 . 1 9 software functions and sample code cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h
46 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 10.5.9 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicates to the host system whether an em- bedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command se- quence. note that the data# polling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. reading data# pol ling status on any word other than the last word to be programmed in the wr ite-buffer-page returns fa lse status information. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comp lete, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi- mately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# po lling produces a ?0? on dq7. when the embed- ded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 47 advance information just prior to the completion of an embedded pr ogram or erase operation, dq7 may change asyn- chronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to vali d data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. see the following for more information: ta b l e 1 0 . 2 0 , write operation status , shows the outputs for data# polling on dq7. figure 10.6 , write operation status flowchart , shows the data# polling algorithm; and figure 14.17 , data# polling timings (during embedded algorithm) , shows the data# polling timing diagram.
48 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information figure 10.6 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 49 advance information dq6: toggle bit i . toggle bit i on dq6 indicates whether an embedded program or erase algo- rithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (pri or to the program or erase operation), and dur- ing the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any ad- dress cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately t pap after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. see the following for additional information: figure 10.6 , write operation status flowchart ; figure 14.18 , toggle bit timings (during embedded algorithm) , and ta b l e 1 0 . 2 0 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii. the ?toggle bit ii? on dq2, when used with dq6, indicates whether a par- ticular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 4 . 1 0 to compare outputs for dq2 and dq6. see the foll owing for additional information: figure 10.6 , the ?dq6: toggle bit i? section, and figures 14.17 ? 14.20 . reading toggle bits dq6/dq2. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typ- ically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then deter- mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the rese t command to return to reading array data. the remaining scenario is that the system initially de termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through succes- sive read cycles, determining the status as descri bed in the previous paragr aph. alternatively, it
50 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 10.6 for more details. note: ? when verifying the status of a write operation (embedded program/erase) of a memory bank, dq6 and dq2 toggle between high and low states in a series of consecutive and con-tiguous status read cycles. in order for this toggling behavior to be properly observed, the consecu- tive status bit reads must not be interleaved with read accesses to other memory banks. if it is not possible to temporarily prevent reads to other memory banks, th en it is recommended to use the dq7 status bit as the alternative meth od of determining the active or inactive sta- tus of the write operation. dq5: exceeded timing limits. dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? ba ck to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been ex ceeded, dq5 produces a ?1.?under both these conditions, the system must write the reset command to return to the read mode (or to the erase- suspend-read mode if a bank was previo usly in the erase-suspend-program mode). dq3: sector erase timeout state indicator. after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase comman d sequence for more details. after the sector erase command is written, the syst em should read the status of dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device accepts additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 0 . 2 0 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort. dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a ?1?. th e system must issue the write to buffer abort reset command sequence to return the device to reading array data. see write buffer program- ming operation for more details.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 51 advance information ta b l e 1 0 . 2 0 write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded eras e operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 a valid address when reading status information. refer to the appropriate subs ection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer pr ogramming operations. note that dq7# during write buffer pro gramming indicates the data-bar for dq7 data for the last loaded write-buffer address location . 6. for any address changes after ce# assertion, re-assertion of ce # might be required after the addresses become stable for data polling during the erase suspend operation using dq2/dq6. program suspend mode ( note 3 ) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data write to buffer ( note 5 ) busy state dq7# to gg l e 0 n/a n/a 0 exceeded timing limits dq7# to gg l e 1 n/a n/a 0 abort state dq7# to gg l e 0 n/a n/a 1
52 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 10.6 simultaneous read/write the simultaneous read/write feature allows the host system to read data from one bank of mem- ory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 14.24 , back-to-back read/write cycle timings , shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc character- istics (cmos compatible) table for read-while-program and read-while-erase current specification. 10.7 writing commands/command sequences when the device is configured for asynchronous read, only asynchronous write operations are allowed, and clk is ignored. when in the synchron ous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. clk and avd# induced address latches are supported in the synchronous programming mode. during a synchronous write oper- ation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynch ronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e s 9.1 ? 9.2 indicate the address space that each sector occupies. the device address space is divided into sixteen banks: banks 1 through 14 co ntain only 64 kword sect ors, while banks 0 and 15 contain both 16 kword boot sectors in addition to 64 kword sectors. a ?bank address? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in ?dc characteristics? represents the active current specification for the write mode. ?ac characteristics-synchronous? and ?ac characteristics-asyn- chronous? contain timing specification tables and timing diagrams for write operations. 10.8 handshaking the handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the rdy (ready) pin, which is a dedicated output and controlled by ce#. when the device is configured to operate in synchronous mode, and oe# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the rdy pin (de- pending on the setting for bit 10 in the configuration register). it is recommended that the host system set cr13?cr11 in the configuration register to the appropriate number of wait states to ensure optimal burst mode operation (see ta b l e 1 0 . 9 , configuration register ). bit 8 in the configuration register allows the host to specify whether rdy is active at the same time that data is ready, or on e cycle before data is ready.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 53 advance information 10.9 hardware reset the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediat ely terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pu lse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the flash memory upon a system reset. see figures 14.5 and 14.12 for timing diagrams. 10.10 software reset software reset is part of the command set (see ta b l e 1 5 . 1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if th e device was previously in erase suspend mode. 5. after any aborted operations note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to the read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignore s reset commands until the operation is com- plete ? the reset command may be written between the cycles in a program command sequence be- fore programming begins (prior to the third cy cle). this resets the bank to which the system was writing to the read mode. ? if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ta b l e 1 0 . 2 1 reset lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
54 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information ? if dq1 goes high during a write buffer pr ogramming operation, the system must write the "write to buffer abort reset" command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com- mand sequence [see the command table for details].
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 55 advance information 11 advanced sector protection/unprotection the advanced sector protection/unprotection feat ure disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware meth- ods, which are independent of each other. th is section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 11.1 . figure 11.1 advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector.
56 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 11.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the dyb orderi ng option. the device programmer or host system must then choose which sector protection method to use. program- ming (setting to ?0?) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) table 11.1 lock register for programming lock register bits refer to ta b l e 1 5 . 2 . notes 1. if the password mode is chosen, the passwor d must be programmed before setting the cor- responding lock register bit. 2. after the lock register bits command set entr y command sequence is written, reads and writes for bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. if both lock bits are selected to be programm ed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection schem e are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sector can operate in any of the following three states: 1. constantly locked. the selected sectors are protected and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described in sections 11.2 ?. 11.2 persistent protection bits the persistent protection bits are unique and nonv olatile for each sector and have the same en- durances as the flash memory. preprogramming an d verification prior to erasure are handled by the device, and therefore do not require system monitoring. device dq15-05 dq4 dq3 dq2 dq1 dq0 s29ws256n 1 1 1 password protection mode lock bit persistent protection mode lock bit customer secsi sector protection bit s29ws128n undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secsi sector protection bit
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 57 advance information notes 1. each ppb is individually programmed and all are erased in parallel. 2. while programming ppb for a sector, array data can be read from any other bank, except bank 0 (used for data# polling) and the bank in which sector ppb is being programmed. 3. entry command disables reads and writes for the bank selected. 4. reads within that bank return the ppb status for that sector. 5. reads from other banks are allowed while writes are not allowed. 6. all reads must be performed using the asynchronous mode. 7. the specific sector address (a23-a14 ws256n, a22-a14 ws128n) are written at the same time as the program command. 8. if the ppb lock bit is set, the ppb program or erase command does not execute and times- out without programming or erasing the ppb. 9. there are no means for individually erasing a specific ppb and no spec ific sector address is required for this operation. 10. exit command must be issued after the execut ion which resets the device to read mode and re-enables reads and writes for bank 0 11. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device as described by the fl ow chart shown in figure 11.2 .
58 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information figure 11.2 ppb program/erase algorithm 11.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unpr otected sectors that have their ppbs cleared (erased to ?1?). by issuing the dyb set or cl ear command sequences, the dybs are set (pro- grammed to ?0?) or cleared (erased to ?1?), thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against in- advertent changes yet does not prevent the ea sy removal of protection when changes are needed. read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail issue reset command exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 59 advance information notes 1. the dybs can be set (programmed to ?0?) or cleared (erased to ?1?) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to ?1?) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to ?1?), then the sectors may be modified depending upon th e ppb state of that sector (see table 11.2 ). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to ?0?). 4. it is possible to have sectors that are persiste ntly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if th ere is a need to change the status of the per- sistently locked sectors, a few more steps ar e required. first, the ppb lock bit must be cleared by either putting the de vice through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired setting s. setting the ppb lock bit once again locks the ppbs, and the device op erates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = v hh as they do when acc =v ih . 11.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programmed to ?0?), it locks all ppbs and when cleared (programmed to ?1?), allows the ppbs to be changed. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to ?0 ?) only after all ppbs are configured to the desired settings. 11.5 password protection method the password protection method allows an even higher level of security than the persistent sector protection mode by requiring a 64 bit password fo r unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set ?0? to maintain the password mode of operation. successful execution of the password unlock command by en- tering the entire password clears the ppb lock bit, allowing for sect or ppbs modifications.
60 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes 1. there is no special addressing order requ ired for programming the password. once the password is written and verified, the password mo de locking bit must be set in order to pre- vent access. 2. the password program command is only capa ble of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out with the cell as a ?0?. 3. the password is all ?1?s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, pr events reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1?a0) are valid during the password read, password program, and password unlock. 9. the exact password must be entered in orde r for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the passwor d mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. 16. if the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read comm ands dyb status, ppb status, and ppb lock status to the device.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 61 advance information figure 11.3 lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s (recommended) pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
62 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information figure 11.2 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bi t is locked (set to ?0?), no changes to the ppbs are allowed. the ppb lock bit can only be unlocke d (reset to ?1?) through a hardware reset or power cycle. see also figure 11.1 for an overview of the advanc ed sector protection feature. 11.6 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp# is at v il , the four outermost sectors are locked (device specific). ? when acc is at v il , all sectors are locked. there are additional methods by which intended or accidental erasure of any sectors can be pre- vented via hardware means. the followi ng subsections describes these methods: 11.6.1 wp# method the write protect feature provides a hardware meth od of protecting the four outermost sectors. this function is provided by the wp# pin and ov errides the previously discussed sector protec- tion/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the ?outermost? boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were la st protected or unprotected. note that the wp# pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 11.6.2 acc method this method is similar to above, except it protects all sectors. once acc input is set to v il , all program and erase functions are disabled and hence all sectors are protected. 11.6.3 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. table 11.2 advanced sector protection software examples unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 63 advance information the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subseque nt writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 11.6.4 write pulse ?glitch protection? noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 11.6.5 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept com- mands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
64 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 12 power conservation modes 12.1 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current cons umption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# in put. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in ?dc characteristics? represents the standby current specification 12.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the auto- matic sleep mode is disabled. note that a new burst operation is required to provide new data. i cc6 in dc characteristics (cmos compatible) represents the automatic sleep mode current specification. 12.3 hardware reset# input operation the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediat ely terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pu lse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 12.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 65 advance information 13 secured silicon sector flash memory region the secured silicon sector provides an extra flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 words in length that consists of 128 words for factory data and 128 wo rds for customer-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the factory indicator bit, dq7, (at autoselect address 03h) is used to indicate whether or not the factory se- cured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? while secured silicon sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secured silicon sector wrap from address ffh back to address 00h. ? reads outside of sector 0 return memory array data. ? continuous burst read past the maximum address is undefined. ? sector 0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is executing an embedded pro- gram or embedded erase algorithm. table 13.1 addresses 13.1 factory secured siliconsector the factory secured silicon sector is always protected when sh ipped from the factory and has the factory indicator bit (dq7) permanently set to a ?1?. this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre programmed with one of the following: ? a random, 8 word secure esn only with in the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion tm program- ming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code programmed through the spansion programming services. spansion programs the customer's code, with or without the random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured silicon sector permanently locked. contact your local representative for details on using spansion programming services. sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
66 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 13.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to ?0?), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is protected, the customer indicator bit is permanently set to ?1.? ? the customer secured silicon sector can be read any number of times, but can be pro- grammed and locked only once. the customer se cured silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the customer secured silicon sector area and none of the bits in th e customer secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when pro- gramming the customer secured silicon sector, but reading in banks 1 through 15 is avail- able. ? once the customer secured silicon sector is lo cked and verified, the system must write the exit secured silicon sector region command se quence which return the device to the mem- ory array at sector 0. 13.3 secured silicon sector entry/exit command sequences the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector re- gion until the system issues the four-cycle exit secured silicon sector command sequence. see command definition tabl e [secured silicon sector command table, appendix table 15.1 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level dr iver user?s guide (available soon on www.amd.com and www.fujits u.com) for general information on spansion flash memory software development guidelines. software functions and sample code
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 67 advance information note: base = base address. /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ note: base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ ta b l e 1 3 . 2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h ta b l e 1 3 . 3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word ta b l e 1 3 . 4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle write base + aaah base + 555h 0090h
68 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14 electrical specifications 14.1 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to + 125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc + 0.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +2.5 v acc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +9.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0. 5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 14.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 14.2 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 14.1 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output ma y be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolut e maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indi cated in the operationa l sections of this data sheet is not implied. exposure of the de vice to absolute maxi mum rating conditions for extended peri ods may affect device reliability. note: the content in this document is adva nce information for the s29ws128n. con- tent in this document is preliminary for the s29w256n. figure 14.1 maximum negative overshoot waveform figure 14.2 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 69 advance information 14.2 operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 v to +1.95 v notes: operating ranges define those limits between which the functionality of the device is guaranteed. 14.3 test conditions table 14.1 test specifications note: the content in this document is advance information for the s29ws128n. con- tent in this document is preliminary for the s29w256n. test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 3.0 @ 54, 66 mhz 2.5 @ 80 mhz ns input pulse levels 0.0?v cc v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v c l device under test figure 14.3 test setup
70 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14.4 key to switching waveforms notes: 1. the content in this document is advance information for the s 29ws128n. content in this document is preliminary for the s29w25 6n. 14.5 switching waveforms 14.6 v cc power-up notes: 1. the content in this document is advance informat ion for the s29ws128n. content in this document is preliminary for the s29w256n. 2. s29ws128n: v cc ramp rate is > 1v/ 100 s and for v cc ramp rate of < 1 v / 100 s a hardware reset is required. figure 14.5 v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 1 ms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs figure 14.4 input waveforms and measurement levels v cc reset# t vcs
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 71 advance information 14.7 dc characteristics (cmos compatible) notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. ce# must be set high wh en measuring the rdy pin. 3. the i cc current listed is typically less than 3.5 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 6. v ih = v cc 0.2 v and v il > ?0.1 v. 7. total current during accelerate d programming is the sum of v acc and v cc currents. 8. v acc = v hh on acc input. 9. the content in this document is advance informatio n for the s29ws128n. conten t in this document is preliminary for the s29w256n. parameter description (notes) test conditions (notes 1 , 8 ) min ty p max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current ( 2 ) v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 27 54 ma 66 mhz 28 60 ma 80 mhz 30 66 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 28 48 ma 66 mhz 30 54 ma 80 mhz 32 60 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 54 mhz 29 42 ma 66 mhz 32 48 ma 80 mhz 34 54 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 32 36 ma 66 mhz 35 42 ma 80 mhz 38 48 ma i cc1 v cc active asynchronous read current ( 3 ) ce# = v il , oe# = v ih , we# = v ih 10 mhz 34 45 ma 5 mhz 17 26 ma 1 mhz 4 7 ma i cc2 v cc active write current ( 4 ) ce# = v il , oe# = v ih , acc = v ih v acc 15a v cc 24 52.5 ma i cc3 v cc standby current ( 5 , 6 ) ce# = reset# = v cc 0.2 v v acc 15a v cc 20 70 a i cc4 v cc reset current ( 6 ) reset# = v il, clk = v il 70 250 a i cc5 v cc active current (read while write) ( 6 ) ce# = v il , oe# = v ih , acc = v ih @ 5 mhz 50 60 ma i cc6 v cc sleep current ( 6 ) ce# = v il , oe# = v ih 270a i acc accelerated program current ( 7 ) ce# = v il , oe# = v ih, v acc = 9.5 v v acc 620ma v cc 14 20 ma v il input low voltage v cc = 1.8 v ?0.5 0.4 v v ih input high voltage v cc = 1.8 v v cc ? 0.4 v cc + 0.4 v v ol output low voltage i ol = 100 a, v cc = v cc min = v cc 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min = v cc v cc v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.4 v
72 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14.8 ac characteristics 14.8.1 clk characterization notes: 1. the content in this document is ad vance information for the s29ws128n. content in this document is preliminary for the s29w256n. 2. not 100% tested. figure 14.6 clk characterization parameter description 54 mhz 66 mhz 80 mhz unit f clk clk frequency max 54 66 80 mhz t clk clk period min 18.5 15.1 12.5 ns t ch clk high time min 7.4 6.1 5.0 ns t cl clk low time t cr clk rise time max 3 3 2.5 ns t cf clk fall time t clk t cl t ch t cr t cf clk
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 73 advance information 14.8.2 synchronous/burst read notes: 1. addresses are latched on the first rising edge of clk. 2. not 100% tested. 3. the content in this document is advance informatio n for the s29ws128n. conten t in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t iacc latency max 80 ns t bacc burst access time valid clock to output delay max 13.5 11.2 9 ns t acs address setup time to clk ( note 1 )min5 4 ns t ach address hold time from clk ( note 1 )min7 6 ns t bdh data hold time from next clock cycle min 4 3 ns t cr chip enable to rdy valid max 13.5 11.2 9 ns t oe output enable to output valid max 13.5 11.2 ns t cez chip enable to high z ( note 2 )max10 ns t oez output enable to high z ( note 2 )max 10 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 5 4 3.5 ns t racc ready access time from clk max 13.5 11.2 9 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 ns t avd avd# pulse min 8 ns f clk minimum clock frequency min 111mhz table 14.2 synchronous wait state requirements max frequency wait state requirement 01 mhz < freq. 14 mhz 2 14 mhz < freq. 27 mhz 3 27 mhz < freq. 40 mhz 4 40 mhz < freq. 54 mhz 5 54 mhz < freq. 67 mhz 6 67 mhz < freq. 80 mhz 7
74 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14.8.3 timing diagrams notes: 1. figure shows total number of wait states set to five cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 14.7 clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 75 advance information notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycl es to seven cycles. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, an d are indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. d8?df in data waveform indicate the order of data within a give n 8-word address range, from lowest to highest. starting addre ss in figure is the 4th address in range (0-f). figure 14.8 8-word linear burst with wrap around notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycl es to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, an d are indicated by rdy. 3. the device is in asynchronous mode with out wrap around. 4. dc?d13 in data waveform indicate the order of data within a gi ven 8-word address range, from lowest to highest. starting addr ess in figure is the 1st address in range (c-13). figure 14.9 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc
76 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has been writte n with cr8=0; device outputs rdy one cycle before valid data. figure 14.10 linear burst with rdy set one cycle before data 14.8.4 ac characterist ics?asynchronous read notes: 1. not 100% tested. 2. the content in this document is advance information for the s29ws128n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t ce access time from ce# low max 80 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 8 ns t aavds address setup time to rising edge of avd# min 4 ns t aavdh address hold time from rising edge of avd# min 7 6 ns t oe output enable to output valid max 13.5 ns t oeh output enable hold time read min 0 ns data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t cas ce# setup time to avd# min 0 ns da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1567 t rdys t bacc t cr ~ ~ ~ ~ ~ ~ ~ ~
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 77 advance information note: ra = read address, rd = read data. figure 14.11 asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas
78 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14.8.5 hardware reset (reset#) notes: 1. not 100% tested. 2. the content in this document is adva nce information for th e s29ws128n. content in this document is preliminary for the s29w256n. figure 14.12 reset timings parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read ( see note )min200ns reset# t rp ce#, oe# t rh
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 79 advance information 14.8.6 erase/program timing notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous program operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous pr ogram operation timing, addresses are latched on the fa lling edge of we#. in sync hronous program operation timing, addresses are latched on the rising edge of clk. 4. see the erase and programming performance section for more information. 5. does not include the preprogramming time. 6. the content in this document is advance information for the s 29ws128n. content in this document is preliminary for the s29w25 6n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t avav t wc write cycle time ( note 1 )min80ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 5ns asynchronous 0 ns t wlax t ah address hold time (notes 2 , 3 ) synchronous min 9 ns asynchronous 20 t avdp avd# low time min 8 ns t dvwh t ds data setup time min 45 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during acce lerated programming) min 1 s t elwl t cs ce# setup time to we# min 5 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avsc avd# setup time to clk min 5 ns t avhc avd# hold time to clk min 5 ns t csw clock setup time to we# min 5 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during erase within a protected sector typ 0 s t psp toggle time during programming within a protected sector typ 0 s
80 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information figure 14.13 chip/sector erase operation timings oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 81 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n) are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is indepe ndent of the set device read mode bit in the configuration register. figure 14.14 program operation timing using avd# oe# ce# data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas
82 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n) are don?t care during command sequence unlock cycles. 4. addresses are latched on the first rising edge of clk. 5. either ce# or avd# is required to go from lo w to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 14.15 program operation timing using clk in relationship to avd# oe# ce# data addresses we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc avd#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 83 advance information note: use setup and hold times from conventional program operation. figure 14.16 accelerated unlock bypass programming timing notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determin e status. when the embedded algorithm operation is completedata# polling outputs true data. figure 14.17 data# polling timings (during embedded algorithm) ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
84 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determin e status. when the embedded algorithm operation is complete, . figure 14.18 toggle bit timings (during embedded algorithm) notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determin e status. when the embedded algorithm operation is complete, . 3. rdy is active with data (d8 = 1 in the configuration register). when d8 = 0 in the configurat ion register, rdy is active one clock cycle before data. figure 14.19 synchronous data polling ti mings/toggle bit timings we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 85 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before da ta (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device not crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are required for ws 5. figure 14.21 latency with boundary crossing when frequency > 66 mhz enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 14.20 dq2 vs. dq6 clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc
86 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before da ta (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are required for ws 5. figure 14.22 latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 87 advance information wait state configuration register setup: d13, d12, d11 = ?111? ? reserved d13, d12, d11 = ?110? ? reserved d13, d12, d11 = ?101? ? 5 programmed, 7 total d13, d12, d11 = ?100? ? 4 programmed, 6 total d13, d12, d11 = ?011? ? 3 programmed, 5 total note: figure assumes address d0 is not at an addr ess boundary, and wait state is set to ?101?. figure 14.23 example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
88 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information note: breakpoints in waveforms indicate th at system may alternately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid information. figure 14.24 back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t ds t dh t oe t as t ah t acc t oeh t wp t ghwl t oez t write cycle t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph t write cycle t read cycle t read cycle
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 89 advance information 14.8.7 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. typical chip programming time is considerably less than the maximum chip programming time listed, and is based on utilizing the write buffer. 4. in the pre-programming step of the embedded eras e algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execut e the two- or four-bus-cycle sequence for the program command. see the appendix for further information on command definitions. 6. contact the local sales office for minimum cycling endu rance values in specific applications and operating conditions. 7. refer to application note ?erase su spend/resume timing? for more details. 8. word programming specification is based upon a sing le word programming operation not utilizing the write buffer. 9. the content in this document is advance informat ion for the s29ws128n. content in this document is preliminary for the s29w256n. parameter ty p ( note 1 )max ( note 2 ) unit comments sector erase time 64 kword v cc 0.6 3.5 s excludes 00h programming prior to erasure ( note 4 ) 16 kword v cc <0.15 2 chip erase time v cc 153.6 (ws256n) 77.4 (ws128n) 308 (ws256n) 154 (ws128n) s acc 130.6 (ws256n) 65.8 (ws128n) 262 (ws256n) 132 (ws128n) single word programming time ( note 8 ) v cc 40 400 s acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time ( note 3 ) v cc 157.3 (ws256n) 78.6 (ws128n) 314.6 (ws256n) 157.3 (ws128n) s excludes system level overhead ( note 5 ) acc 100.7 (ws256n) 50.3 (ws128n) 201.3 (ws256n) 100.7 (ws128n)
90 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 14.8.8 bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c; f = 1.0 mhz. 3. the content in this document is advance informatio n for the s29ws128n. conten t in this document is preliminary for the s29w256n. parameter symbol parameter description te s t s e t u p ty p . max unit c in input capacitance v in = 0 5.3 6.3 pf c out output capacitance v out = 0 5.8 6.8 pf c in2 control pin capacitance v in = 0 6.3 7.3 pf
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 91 advance information 15 appendix this section contains information relating to soft ware control or interfacing with the flash device. for additional information and assistance regarding software, see the additional resources sec- tion on page 23, or explore the web at www.amd.com and www.fujitsu.com.
92 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information table 15.1 memory array commands command sequence (notes) cycles bus cycles (notes 1?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read ( 6 )1 ra rd reset ( 7 ) 1 xxx f0 auto- select ( 8 ) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id ( 9 ) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e ba+x0e data ba+x0f 2200 indicator bits ( 10 ) 4 555 aa 2aa 55 [ba]555 90 [ba]x03 data program 4 555 aa 2aa 55 555 a0 pa pd write to buffer ( 11 ) 6 555 aa 2aa 55 pa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 12 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend ( 13 ) 1 ba b0 erase/program resume ( 14 ) 1 ba 30 set configuration register ( 18 ) 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr cfi query ( 15 ) 1 [ba]555 98 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program ( 16 ) 2 xxx a0 pa pd cfi ( 16 ) 1 xxx 98 reset 2 xxx 90 xxx 00 secured silicon sector entry 3 555 aa 2aa 55 555 88 program ( 17 ) 4 555 aa 2aa 55 555 a0 pa pd read ( 17 )1 00 data exit ( 17 ) 4 555 aa 2aa 55 555 90 xxx 00 legend: x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of the avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. ws256n = a23?a14; ws128n = a22?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20. cr = configuration register data bits d15?d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 10.1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specifie d in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 6. no unlock or command cycles required when bank is reading array data. 7. reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autosele ct mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the system must provide the bank address. see autoselect section for more information . 9. data in cycle 5 is 2230 (ws256n) or 2231 (ws128n). 10. see table 10.9 for indicator bit values. 11. total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. command sequence resets device for next command after write- to-buffer operation. 13. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. erase resume command is valid only during the erase suspend mode, and requires the bank address. 15. command is valid when device is ready to read array data or when device is in autoselect mode. address equals 55h on all future devices, but 555h for ws256n/128n. 16. requires entry command sequence prior to execution. unlock bypass reset command is required to return to reading array data. 17. requires entry command sequence prior to execution. secured silicon sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. requires reset command to configure the configuration register.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 93 advance information table 15.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry (5) 3 555 aa 2aa 55 555 40 program (6, 12) 2 xx a0 77/00 data read (6) 1 77 data command set exit (7) 2 xx 90 xx 00 password protection command set entry (5) 3 555 aa 2aa 55 555 60 program [0-3] (8) 2 xx a0 00 pwd[0-3] read ( 9 )4 0...00 pwd0 0...01 pwd1 0...02 pwd2 0...03 pwd3 unlock 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit (7) 2 xx 90 xx 00 non-volatile sector protection (ppb) command set entry (5) 3 555 aa 2aa 55 [ba]555 c0 ppb program (10) 2 xx a0 sa 00 all ppb erase (10, 11) 2 xx 80 00 30 ppb status read 1 sa rd(0) command set exit (7) 2 xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry (5) 3 555 aa 2aa 55 [ba]555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 ba rd(0) command set exit (7) 2 xx 90 xx 00 volatile sector protection (dyb) command set entry (5) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit (7) 2 xx 90 xx 00 l egen d : x = don?t care. ra = address of the memory location to be read. pd(0) = secured silicon sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lock bit. pd(1), or bit[1], must be set to ?0? for protection while pd (2), bit[2] must be left as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd (1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = sector address. ws 256n = a23?a14; ws128n = a22?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0), rd(1), rd(2) = dq0, dq1, or dq2 protection indicator bit. if protected, dq0, dq1, or dq2 = 0. if unprotected, dq0, dq1, dq2 = 1. notes: 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specifie d in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. if both the persistent protection mode locking bit and the password protection mode locking bit are set at the same time, the command operation aborts and returns the device to the default persistent sector protection mode during 2nd bus cycle. note that on all future devices, addresses equal 00h, but is currently 77h for the ws256n only. see tables 11.1 and 11.2 for explanation of lock bits. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. see figure 11.2 for details. 11. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure. 12. the second cycle address for the lock register program operation is 77 for s29ws256n; however, for ws128n this address is 00.
94 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 15.1 common flash me mory interface the common flash interface (cfi) specification outlines device and host system software inter- rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen- dent, and forward- and back-ward-compatible fo r the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read array data. the system can read cfi in- formation at the addresses given in tables 15.3?15.6 ) within that bank. all reads outside of the cfi address range, within the bank, returns non- valid data. reads from other banks are allowed, writes are not. to terminate reading cfi da ta, the system must write the reset command. the following is a c source code example of using the cfi entry and exit functions. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, please refer to the cfi specification (see jedec publications jep137-a and jesd68.01and cfi publication 100). please contact your sales office for copies of these documents. ta b l e 1 5 . 3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 15.4 system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0004h max. timeout for buffer write 2 n times typical 25h 0003h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 95 advance information ta b l e 1 5 . 5 device geometry definition addresses data description 27h 0019h (ws256n) 0018h (ws128n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws256n) 007dh (ws128n) erase block region 2 information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
96 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information ta b l e 1 5 . 6 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0100h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0100 = 0.11 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00f3h (ws256n) 007bh (ws128n) simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = dual boot device 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0007h secured silicon sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n ns 56h 0005h program suspend time-out maximum 2 n ns 57h 0010h bank organization: x = number of banks 58h 0013h (ws256n) 000bh (ws128n) bank 0 region information. x = number of sectors in bank 59h 0010h (ws256n) 0008h (ws128n) bank 1 region information. x = number of sectors in bank
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 97 advance information 5ah 0010h (ws256n) 0008h (ws128n) bank 2 region information. x = number of sectors in bank 5bh 0010h (ws256n) 0008h (ws128n) bank 3 region information. x = number of sectors in bank 5ch 0010h (ws256n) 0008h (ws128n) bank 4 region information. x = number of sectors in bank 5dh 0010h (ws256n) 0008h (ws128n) bank 5 region information. x = number of sectors in bank 5eh 0010h (ws256n) 0008h (ws128n) bank 6 region information. x = number of sectors in bank 5fh 0010h (ws256n) 0008h (ws128n) bank 7 region information. x = number of sectors in bank 60h 0010h (ws256n) 0008h (ws128n) bank 8 region information. x = number of sectors in bank 61h 0010h (ws256n) 0008h (ws128n) bank 9 region information. x = number of sectors in bank 62h 0010h (ws256n) 0008h (ws128n) bank 10 region information. x = number of sectors in bank 63h 0010h (ws256n) 0008h (ws128n) bank 11 region information. x = number of sectors in bank 64h 0010h (ws256n) 0008h (ws128n) bank 12 region information. x = number of sectors in bank 65h 0010h (ws256n) 0008h (ws128n) bank 13 region information. x = number of sectors in bank 66h 0010h (ws256n) 0008h (ws128n) bank 14 region information. x = number of sectors in bank 67h 0013h (ws256n) 000bh (ws128n) bank 15 region information. x = number of sectors in bank table 15.6 primary vendor-specific extended query (continued) addresses data description
98 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 16 commonly used terms te r m d e f i n i t i o n acc accelerate. a special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above v cc . in some devices acc may protect all sectors when at a low voltage. a max most significant bit of the address inpu t [a23 for 256mbit, a22 for128mbit, a21 for 64mbit] a min least significant bit of the address input si gnals (a0 for all devices in this document). asynchronous operation where signal relationships are ba sed only on propagation delays and are unrelated to synchronous control (clock) signal. autoselect read mode for obtaining manufacturer and device information as well as sector protection status. bank section of the memory array consisting of multiple consecutive sectors. a read operation in one bank, can be independen t of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. boot sector smaller size sectors located at the top and or bottom of flash device address space. the smaller sector size allows for finer gra nularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. boundary location at the beginning or end of series of memory locations. burst read see synchronous read . byte 8 bits cfi common flash interface. a flash memory in dustry standard specification [jedec 137- a and jesd68.01] designed to allow a system to interrogate the flash to determine its size, type and other performance parameters. clear zero (logic low level) configuration register special purpose register which must be programmed to enable synchronous read mode continuous read synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address erase returns bits of a flash memory array to th eir default state of a logical one (high level). erase suspend/erase resume halts an erase operation to allow reading or programming in any sector that is not selected for erasure bga ball grid array package. spansion llc offers two variations: fortified ball grid array and fine-pitch ball grid array. see the spec ific package drawing or connection diagram for further details. linear read synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address . mcp multi-chip package. a method of combining in tegrated circuits in a single package by stacking multiple die of the same or different devices. memory array the programmable area of the product available for data storage. mirrorbit? technology spansion? trademarked technology for storin g multiple bits of data in the same transistor.
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 99 advance information page group of words that may be accessed more ra pidly as a group than if the words were accessed individually. page read asynchronous read operation of several wo rds in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. different words in the group are accessed by changing only the least significan t address lines. password protection sector protection method wh ich uses a programmable passw ord, in addition to the persistent protection method , for protection of sectors in the flash memory device . persistent protection sector protection method that uses comm ands and only the standard core voltage supply to control protection of sectors in the flash memory device. this method replaces a prior technique of requiring a 12v supply to control th e protection method. program stores data into a flash memory by selectiv ely clearing bits of the memory array in order to leave a data pattern of ones and zeros . program suspend/program resume halts a programming operation to read data from any location that is not selected for programming or erase. read host bus cycle that causes the flash to output data onto the data bus. registers dynamic storage bits for holding device cont rol information or tracking the status of an operation. secured silicon secured silicon. an area co nsisting of 256 bytes in which any word may be programmed once, and the entire area ma y be protected once from any future programming. information in this area may be programmed at the factory or by the user. once programmed and protected ther e is no way to change the secured information. this area is often used to store a software readable identification such as a serial number. sector protection use of one or more control bi ts per sector to indicate whether each sector may be programmed or erased. if the protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. sector an area of the memory array in which all bi ts must be erased together by an erase operation. simultaneous operation mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operat ion may then proceed while the host immediately follows the embedded algorith m command with reading from another bank. reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. synchronous operation operation that progresses only when a timi ng signal, known as a clock, transitions between logic levels (that is, at a clock edge). versatileio? (v io ) separate power supply or voltage reference si gnal that allows the host system to set the voltage levels that the device genera tes at its data outputs and the voltages tolerated at its data inputs. unlock bypass mode that facilitates faster program time s by reducing the number of command bus cycles required to issue a write operation co mmand. in this mode th e initial two unlock write cycles, of the usual 4 cycle program command, are not required ? reducing all program commands to two bus cycles while in this mode. word two contiguous bytes (16 bits) located at an even byte boundary. a double word is two contiguous words located on a two word boundary. a quad word is four contiguous words located on a four word boundary. te r m d e f i n i t i o n
100 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information wraparound special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last byte or word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. write interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. the term write is often associated with writing command cycles to enter or exit a particular mode of operation. write buffer multi-word area in which multiple words may be programmed as a single operation . a write buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. write buffer programming method of writing multiple words, up to the maximum size of the write buffer, in one operation. using write buff er programming results in 8 times faster programming time than by using single word at a time programming commands. write operation status allows the host system to determine the status of a program or erase operation by reading several special purpose register bits . te r m d e f i n i t i o n
publication number s71ws-n_01 revision a amendment 4 issue date september 15, 2005 advance information 1.8v psram type 4 4m x 16-bit synchronous burst psram features ? process technology: cmos ? organization: 4m x16 bit ? power supply voltage: 1.7~2.0v ? three state outputs ? supports mrs (mode register set) ? mrs control - mrs pin control ? supports power saving modes - partial array refresh mode internal tcsr ? supports driver strength optimization for system environment power saving ? supports asynchronous 4-page read and asynchronous write operation ? supports synchronous burst read and asynchro nous write operation (address latch type and low adv# type) ? supports synchronous burst read and synchronous burst write operation ? synchronous burst (read/write) operation ? supports 4 word / 8 word / 16 word and full page(256 word) burst ? supports linear burst type & interleave burst type ? latency support: latency 5 @ 66 mhz(t cd 10ns) latency 4 @ 54 mhz(t cd 10ns) ? supports burst read suspend in no clock toggling ? supports burst write data masking by /ub & /lb pin control ? supports wait# pin function for indicating data availability. ? max. burst clock frequency: 66 mhz
102 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 17 pin description pin name function type description clk clock input commands, data are referenced to clk adv# address valid address valid from adv# falling edge to adv# rising edge mrs# mode register set mrs# enables mode register to be set. addresses are loaded as mode setting is low cs# chip select cs# enables the chip to start operating when low cs# disables the chip and puts it into standby mode when high cs# stops burst operating.during burst operation when high oe# output enable oe# enables the ch ip to output the data when low we# write enable we# enables the chip to start writing the data when low lb# lower byte (i/o 0~7 ) ub# (or lb#) enables upper byte (or lower byte) to be operated when low ub# upper byte (i/o 8~15 ) a0-a21 address 0 ~ address 21 valid addresses input when adv# is low. mode setting inputs during mrs# low. i/o0-i/o15 data inputs / outputs input/output depending on ub# or lb# status, word (16-bit, ub#, and lb# low) data, upper byte (8-bit, ub# low & lb# high) data or lo wer byte (8-bit, lb# low, and ub# high) data is loaded v cc core voltage source power power supply for cells and circuits except for i/o buffer circuits v ccq i/o voltage source power power supply for i/o buffer circuits v ss core ground source gnd ground for cells and circuits except for i/o buffer circuits v ssq i/o ground source gnd ground for i/o buffer circuits wait# valid data indicator output wait# indica tes that output data is invalid when low dnu do not use ? ?
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 103 advance information 18 functional block diagram 19 power up sequence after applying v cc up to minimum operating voltage (1.7 v), drive cs# high first and then drive mrs# high. this gets the device into power up mode. wait for a minimum of 200 s to get into the normal operation mode. during power up mo de, the standby current cannot be guaranteed. to obtain stable standby current levels, at least one cycle of active operation should be imple- mented regardless of wait time duration. to obtain appropriate device operat ion, be sure to follow the power up sequence. 1. apply power. 2. maintain stable power (v cc min.=1.7 v) for a minimum 200 s with cs# and mrs# high. row select data controller vcc vss precharge circuit. memory array column select row addresses column addresses clk data controller data controller i/o0~i/o7 i/o8~i/o15 adv# mrs# cs# oe# we# ub# lb# wait# control logic clk generator i/o circuit
104 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 20 power up and standby mode timing diagrams 20.1 power up note: after v cc reaches v cc (min.), wait 200 s with cs# and mrs# high. this puts the device into normal operation. figure 20.1 power up timing 20.2 standby mode figure 20.2 standby mode state machines the default mode after power up is asynchronous mode (4 page read and asynchronous write). but this default mode is not 100% guaranteed, so the mrs# setting sequence is highly recom- mended after power up. for entry to par mode, drive the mrs# pin into v il for over 0.5s (suspend period) during standby mode after the mrs# setting has been completed (a4=1, a3=0). if the mrs# pin is driven into v ih during par mode, the device reverts to standby mode without the wake up sequence. ~ ~ v cc v cc(min) min. mrs# cs# min. 0ns power up mode min. 0ns normal operation 200 s 200 s ~ ~ ~ ~ active standby mode par mode mrs setting cs# = v ih mrs# = v ih cs# = ub# = lb# = v il we# = v il , mrs# = v ih cs# = v il , ub# or lb# = v il mrs# = v ih cs# = v ih mrs# = v ih mrs# = v il cs# = v il we# = v il , mrs#=v il mrs setting initial state (wait 200 s) power on
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 105 advance information 21 functional description table 21.1 asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) legend: x = don?t care (must be low or high state). notes: 1. in asynchronous mode, clock and adv# are ignored. 2. the wait# pin is high-z in asynchronous mode. ta b l e 2 1 . 2 synchronous burst read & asynchronous write mode (a15/a14=0/1) notes: 1. x must be low or high state. 2. x means don?t care (can be low, high or toggling). 3. wait# is the device output signal and does not have any a ffect on the mode definition. pl ease refer to each timing diagram for wait# pin function. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 power deselected h h x x x x high-z high-z standby deselected h l x x x x high-z high-z par output disabled l h h h x x high-z high-z active outputs disabled l h x x h h high-z high-z active lower byte read l h l h l h d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l h h l l h d in high-z active upper byte write l h h l h l high-z d in active word write l h h l l l d in d in active mode register set l l h l l l high-z high-z active mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x ( note 1 ) x ( note 1 ) x ( note 1 ) x ( note 1 ) high- z high- z x (note 2) x (note 2) standby deselected h l x ( note 1 ) x ( note 1 ) x ( note 1 ) x ( note 1 ) high- z high- z x (note 2) x (note 2) par output disabled lh h h x ( note 1 ) x ( note 1 ) high- z high- z x (note 2) hactive outputs disabled lh x ( note 1 ) x ( note 1 ) hh high- z high- z x (note 2) hactive read command lh x ( note 1 ) h x ( note 1 ) x ( note 1 ) high- z high- z active lower byte read lh l h l h d out high- z hactive upper byte read lh l h h l high- z d out hactive word read l h l h l l d out d out hactive lower byte write lh h l l h d in high- z x (note 2) active upper byte write lh h l h l high- z d in x (note 2) active word write l h h l l l d in d in x (note 2) active mode register set ll h l l l high- z high- z x (note 2) active or or or or
106 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information ta b l e 2 1 . 3 synchronous burst read & synchronous burst write mode(a15/a14 = 1/0) notes: 1. x must be low or high state. 2. x means ?don?t care? (can be low, high or toggling). 3. wait# is the device output signal and does not have any a ffect on the mode definition. pl ease refer to each timing diagram for wait# pin function. 4. the last data written in the previous asynchronous write mode is not valid. to make the lastly written data valid, implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the transition from synchronous burst write operation to asynchronous write operation is prohibited. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x ( note 1 ) x ( note 1 ) x ( note 1 ) x ( note 1 ) high-z high-z x ( note 2 ) x ( note 2 ) standby deselected h l x ( note 1 ) x ( note 1 ) x ( note 1 ) x ( note 1 ) high-z high-z x ( note 2 ) x ( note 2 ) par output disabled l h h h x x high-z high-z x ( note 2 ) hactive outputs disabled lh x ( note 1 ) x ( note 1 ) h h high-z high-z x ( note 2 ) hactive read command lh x ( note 1 ) h x x high-z high-z active lower byte read lh l h l h d out high-z h active upper byte read lh l h h l high-zd out hactive word read l h l h l l d out d out hactive write command lh x ( note 1 ) high-z high-z active lower byte write lh h x ( note 1 ) lhd in high-z h active upper byte write lh h x ( note 1 ) hlhigh-zd in hactive word write l h h x ( note 1 ) lld in d in hactive mode register set l l h l l high-z high-z active or l or l
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 107 advance information 22 mode register setting operation the device has several modes: ? asynchronous page read mode ? asynchronous write mode ? synchronous burst read mode ? synchronous burst write mode ? standby mode ? partial array refresh (par) mode. partial array refresh (par) mode is defined through the mode register set (mrs) option. the mrs option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode. 22.1 mode regist er set (mrs) the mode register stores the data for controlling the various operation modes of this device. it programs partial array refresh (par), burst length, burst type, latency count and various vendor specific options to make psram type 4 useful for a variety of different applications. the default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. the mode register is written by driving cs#, adv#, we#, ub#, lb# and mrs# to v il and driving oe# to v ih during valid addressing. the mode register is divided into various fields depending on the fields of functions. the par field uses a0~a4, burst length field uses a5~a7, burst type uses a8, latency count uses a9~a11, wait polarity uses a13, operation mode uses a14~a15 and driver strength uses a16~a17. refer to ta b l e 2 2 . 1 for detailed mode register settings. a18~a22 addresses are don?t care in the mode register setting. table 22.1 mode register setting according to field of function note: ds (driver strength), ms (mod e select), wp (wait polarity), latency (latency count), bt (burst type), bl (burst length), par (partial array refresh), para (partial array refresh array), pars (par tial array refresh size), rfu (reserved for future use). table 22.2 mode register set address a17 ? a16 a15 ? a14 a13 a12 a11 ? a9 a8 a7 ? a5 a4 ? a3 a2 a1 ? a0 function ds ms wp rfu latency bt bl par para pars driver strength mode select a17 a16 ds a15 a14 ms 0 0 full drive (default) 0 0 async. 4 page read / async. write (default) 0 1 1/2 drive 0 1 sync. burst read / async. write 1 0 1/4 drive 1 0 sync. burst read / sync. burst write wait# polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl 0 low enable (default) 0 must (default) 0 0 0 3 0 linear (default) 0 1 0 4 word 1 high enable 1 ? 0 0 1 4 1 interleave 0 1 1 8 word 010 5 (default) 100 16 word (default) 0 1 1 6 1 1 1 full (256 word)
108 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information note: the address bits other than those listed in the table above are reserved. for exam ple, burst length address bits(a7:a6:a5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. if the reserve d address bits are input, then the mode will be set to the default mode. each field has its ow n default mode as indicated. a12 is a reserved bit for future use. a12 must be set as 0 . not all the mode settings are tested. per the mode settings to be tested, please contact spansion. the 256 word full page bu rst mode needs to meet t bc (burst cycle time) parameter as max. 2500 ns. the last data written in the previous asynchronous write mode is not valid. to make the lastly written data valid, implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the transition from synchronous burst write operation to asynchronous write operation is prohibited. 22.2 mode register setting timing in this device, the mrs# pin is used for two purposes. one is to get into the mode register setting and the other one is to execute partial array refresh mode. to get into the mode register setting, the system must drive mrs# pin to v il and immediately (within 0.5s) issue a write command (drive cs#, adv#, ub#, lb# and we# to v il and drive oe# to v ih during valid address). if the subsequent write command (we# signal input) is not issued within 0.5s, then the device might get into the par mode. this device supports software access control type mode register setting timing. this timing consists of 5 cycles of read operation. each cycle of read operation is normal asynchronous read operation. clock and adv# are don?t care and wait# signal is high-z. cs# should be toggling between cycles. the address for 1st, 2nd and 3rd cycle should be 3fffff(h) and the address for 4th cycle should be 3ffeff. the address for 5th cycle should be mrs code (register setting values). figure 22.1 pin mrs timing waveform (oe# = v ih ) partial array refresh par array par size a4 a3 par a2 para a1 a0 pars 1 0 par enable 0 bottom array (default) 0 0 full array (default) 1 1 par disable (default) 1 top array 0 1 3/4 array 1 0 1/2 array 1 1 1/4 array t wu address we# t wc t cw t aw t bw t wp t as cs# t mw adv# mrs# ub#, lb# register write start register write complete register update complete
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 109 advance information notes: 1. mrs#= vih, clk = adv# = ub# = lb# = don?t care, wait# = high-z. 2. do not allow this timing to occur during normal operation. figure 22.2 software mrs timing waveform table 22.3 mrs ac characteristics note: v cc =1.7~2.0v, t a =-40 to 85c, maximum main clock frequency=66mhz. parameter list symbol speed units min max mrs mrs# enable to register write start t mw 0 500 ns end of write to mrs# disable t wu 0 ? ns read cycle time t rcm 70 ? ns cs# high pulse width t chm 10 ? ns cs# low pulse width t clm 60 ? ns t rcm t chm t clm 3fffff 3fffff 3fffff 3ff e ff mrs code address cs# oe# we#
110 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 23 asynchronous operation 23.1 asynchronous 4 page read operation asynchronous normal read operation starts wh en cs#, oe# and ub# or lb# are driven to v il under the valid address without toggling page addr esses (a0, a1). if the page addresses (a0, a1) are toggled under the other valid address, the firs t data will be out with the normal read cycle time (t rc ) and the second, the third and the fourth data will be out with the page cycle time (t pc ). (mrs# and we# should be driven to v ih during the asynchronous (page) read operation) clock, adv#, wait# signals are ignored during th e asynchronous (page) read operation. 23.2 asynchronous write operation asynchronous write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid address. mrs# and oe# should be driven to v ih during the asynchronous write operation. clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. 23.3 asynchronous write oper ation in synchronous mode a write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid ad- dress. clock input does not have any affect to the write operation (mrs# and oe# should be driven to v ih during write operation. adv# can be either toggling for address latch or held in v il ). clock, adv#, and wait# signals are ignored duri ng the asynchronous (page) read operation. figure 23.1 asynchronous 4-page read figure 23.2 asynchronous write a1~a0 cs# oe# a22~a2 ub#, lb# data out high-z high- z high-z address cs# we# data in data out ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 111 advance information 24 synchronous burst operation burst mode operations enable the system to get high performance read and write operation. the address to be accessed is latched on the rising edge of clock or adv# (whichever occurs first). cs# should be setup before the address latch. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# high) or a write (we# low). for the optimized burst mode of each system, the system should determine how many clock cy- cles are required for the first data of each burst access (latency count), how many words the device outputs during an access (burst length) and which type of burst operation (burst type: linear or interleave) is needed. the wait polarity should also be determined (see ta b l e 2 2 . 2 ). 24.1 synchronous burst read operation the synchronous burst read command is implemented when the clock rising is detected during the adv# low pulse. adv# and cs# should be se t up before the clock rising. during the read command, we# should be held in v ih . the multiple clock risings (during the low adv# period) are allowed, but the burst operation starts from the first clock rising. the first data will be out with latency count and t cd . 24.2 synchronous burst write operation the synchronous burst write command is implemented when the clock rising is detected during the adv# and we# low pulse. adv#, we# and cs# should be set up before the clock rising. the multiple clock risings (during the low adv# peri od) are allowed but, the burst operation starts from the first clock rising. the first data w ill be written in the latency clock with t ds . note: latency 5, bl 4, wp: low enable figure 24.1 synchronous burst read note: latency 5, bl 4, wp: low enable figure 24.2 synchronous burst write clk adv# addr. oe# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ub#, lb# wait# data out clk adv# addr . we# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 wait# data in ub#, lb#
112 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 25 synchronous burst operation terminology 25.1 clock (clk) the clock input is used as the reference for sy nchronous burst read and write operation of the psram type 4. the synchronous burst read and wr ite operations are synchronized to the rising edge of the clock. the clock transitions must swing between v il and v ih . 25.2 latency count the latency count configuration tells the device how many clocks must elapse from the burst command before the first data should be availabl e on its data pins. this value depends on the input clock frequency. ta b l e 2 5 . 1 shows the supported latency count. table 25.1 latency count support ta b l e 2 5 . 2 number of clocks for 1st data note: the first data will always keep the latency. from the second data on, some period of wait time may be caused by wait# pin. figure 25.1 latency configuration (read) 25.3 burst length burst length identifies how many data the device outputs during an access. the device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word full page burst mode needs to meet t bc (burst cycle time) para meter as 2500 ns max. the first data will be output with the set latency + t cd . from the second data on, the data will be output with t cd from each clock. clock frequency up to 66 mhz up to 54 mhz up to 40 mhz latency count 543 set latency latency 3 latency 4 latency 5 # of clocks for 1st data (read) 456 # of clocks for 1st data (write) 234 address data out adv# clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 113 advance information 25.4 burst stop burst stop is used when the system wants to stop burst operation on purpose. if driving cs# to v ih during the burst read operation, then the burs t operation is stopped. during the burst read operation, the new burst operation cannot be issu ed. the new burst operatio n can be issued only after the previous burst operation is finished. the burst stop feature is very useful because it enables the user to utilize the unsupported burst length such as 1 burst or 2 burst, used mostly in the mobile handset application environment. 25.5 wait control (wait#) the wait# signal indicates to the host system when it?s data-out or data-in is valid. to be compatible with the flash interfaces of various microprocessor types, the wait# polarity (wp) can be configured. the polarity can be programmed to be either low enable or high enable. for the timing of the wait# signal, it should be set active one clock prior to the data regardless of read or write cycle. note: latency: 5, burst length: 4, wp: low enable figure 25.2 wait# and read/write latency control 12345678910111213 adv# read clk dq0 dq1 0 dq2 write d0 d1 d2 dq3 d3 data out data in cs# latency 5 latency 5 high-z wait# high-z wait#
114 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 25.6 burst type the device supports linear type burst sequence and interleave type burst sequence. linear type burst sequentially increments the burst address from the starting address. the detailed linear and interleave type burst address sequence is shown in ta b l e 2 5 . 3 . ta b l e 2 5 . 3 burst sequence notes: 1. wrap: burst address wraps within word boundary and ends after fulfilled the burst length. 2. 256 word full page burst mode needs to meet t bc (burst cycle time) parameter as max. 2500 ns. start address burst address sequence (decimal) wrap ( note 1 ) 4 word burst 8 word burst 16 word burst full page(256 word) linear interleave linear interleave linear interleave linear 0 0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1 -2-...-14-15 0-1-2-3-4...14-15 0-1-2-...-254-255 1 1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6 1 -2-3-...-15-0 1-0-3-2-5...15-14 1-2-3-...-255-0 2 2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5 2-3-4-...-0-1 2-3-0-1-6...12-13 2-3-4-...-255-0-1 3 3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4 3-4-5-...-1-2 3-2-1-0-7...13-12 3-4-5-...-255-0-1-2 4 4-5-...-1-2-3 4-5-6-...-2-3 4-5-6-...-2-3 4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3 5 5-6-...-2-3-4 5-4-7-...-3-2 5-6-7-...-3 -4 5-4-7-6-1...11-10 5-6-7-...-255-...-3-4 6 6-7-...-3-4-5 6-7-4-...-0-1 6-7-8-...-4-5 6-7-4-5-2...8-9 6-7-8-...-255-...-4-5 7 7-0-...-4-5-6 7-6-5-...-1-0 7-8-9-...-5-6 7-6-5-4-3...9-8 7-8-9-...-255-...-5-6 ~~~~ 14 14-15-0-...-12-13 14-15-12-...-0-1 14-15-...-255-...-12-13 15 15-0-1-...-13-14 15-14-13-...-1-0 15-16-...-255-...-13-14 ~ ~ 255 255-0-1-...-253-254
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 115 advance information 26 low power features 26.7 partial array refresh (par) mode the par mode enables the user to specify the active memory array size. this device consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays through the mode register setting. the active memory array is periodically refreshed whereas the disabled array is not refreshe d, so the previously stored data is lost. even though par mode is enabled through the mode register setting, par mode execution by the mrs# pin is still needed. the normal operation can be executed even in refresh-disabled array as long as the mrs# pin is not driven to the low condition for over 0.5 s. driving the mrs# pin to the high condition puts the device back to the normal operation mode from the par executed mode. refer to figure 26.1 and ta b l e 2 6 . 1 for par operation and par address mapping. figure 26.1 par mode execution and exit table 26.1 par mode characteristics notes: 1. only the data in the refreshed block are valid. 2. the par array can be selected through mode register set (see mode register setting operation ). 26.8 driver strength optimization the optimization of output driver strength is po ssible through the mode register setting to adjust for the different data loadings. through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. the device supports full drive, 1/2 drive and 1/4 drive. 26.1 internal tcsr the internal temperature compensated self refresh (tcsr) feature is a very useful tool for re- ducing standby current at room temperature (b elow 40c). dram cells have weak refresh characteristics in higher temperatures. high temp eratures require more refresh cycles, which can lead to standby current increase. without the internal tcsr, the refresh cycle should be set at worst condition so as to cover the high temperature (85c) refresh characteristics. but with internal tcsr, a refresh cycle below 40c can be optimized, so the standby current at room temperature can be greatly reduced. this feature is beneficial si nce most mobile phones are used at or below 40c in the phone standby mode. power mode address (bottom array) ( note 2 ) address (top array) ( note 2 ) memory cell data standby current (a, max) wait time (s) standby (full array) 000000h ~ 3fffffh 000000h ~ 3fffffh valid ( note 1 ) tbd 0 partial refresh(3/4 block) 000000h ~ 2fffffh 100000h ~ 3fffffh tbd partial refresh(1/2 block) 000000h ~ 1fffffh 200000h ~ 3fffffh tbd partial refresh(1/4 block) 000000h ~ 0fffffh 300000h ~ 3fffffh tbd mrs# mode cs# normal operation 0.5 s suspend par mode normal operation
116 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 27 absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. functional operation should be restricted to use under recommended operating conditions only. exposure to absolute maxi - mum rating conditions longer than one second may a ffect reliability. 28 dc recommended operating conditions notes: 1. ta=-40 to 85c, unle ss otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. 29 capacitance (ta = 25c, f = 1 mhz) note: capacitance is sampled, not 100% tested. item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 v to v cc +0.3 v v power supply voltage relative to v ss v cc -0.2 v to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c symbol parameter min typ max unit v cc power supply voltage 1.7 1.85 2.0 v v ss ground 0 0 0 v ih input high voltage 0.8 x v cc ?v cc + 0.2 (note 2) v il input low voltage -0.2 (note 3) ?0.4 symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c io input/output capacitance v out = 0v ? 10 pf
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 117 advance information 30 dc and operating characteristics 30.1 common notes: 1. full array partial refresh current (i sbp ) is the same as standby current (i sb1 ). 2. standby mode is supposed to be set up after at least one active operation after power up. isb1 is measured 60 ms from the time when standby mode is set up. 31 ac operating conditions 31.1 test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 31.1 ): cl=30pf figure 31.1 par mode execution and exit item symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs#=v ih , mrs#=v ih , oe#=v ih or we#=v il , v io =v ss to v cc -1 ? 1 a average operating current i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs#=v il , mrs#=v ih , v in =v il or v ih ? ? 40 ma average operating current (sync) i cc3 burst length 4, latency 5, 66mhz, iio=0ma, address transition 1 time, cs#=v il , mrs#=v ih , v in =v il or v ih 40 ma output low voltage v ol i ol =0.1ma ? ? 0.2 v output high voltage v oh i oh =-0.1ma 1.4 ? ? v standby current (cmos) i sb1 ( note 2 ) cs# v cc -0.2v, mrs# v cc -0.2v, other inputs = v ss to v cc < 40c ? ? 120 a < 85c ? ? 180 a partial refresh current i sbp ( note 1 ) mrs# 0.2v, cs# v cc -0.2v other inputs = v ss to v cc < 40c 3/4 block ? ? 120 a 1/2 block ? ? 115 1/4 block ? ? 115 < 85c 3/4 block ? ? 180 a 1/2 block ? ? 165 1/4 block ? ? 165 50 dout 30pf z0= 50 vtt = 0.5 x v ddq
118 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 31.2 asynchronous ac characteristics (v cc =1.7~2.0v, t a =?40 to 85 c) note: t wp (min)=70ns for continuous write operation over 50 times. symbol parameter speed unit min max aysnc (page) read t rc read cycle time 70 ? ns t pc page read cycle time 25 ? ns t aa address access time ? 70 ns t pa page access time ? 20 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 35 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 5 ? ns t olz output enable to low-z output 5 ? ns t chz chip disable to high-z output 0 12 ns t bhz ub#, lb# disable to high-z output 0 12 ns t ohz output disable to high-z output 0 12 ns t oh output hold 3 ? ns async write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t adv adv# minimum low pulse width 7 ? ns t as address set-up time to beginning of write 0 ? ns t as(a) address set-up time to adv# falling 0 ? ns t ah(a) address hold time from adv# rising 7 ? ns t css(a) cs# setup time to adv# rising 10 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 (note 1) ? ns t whp we# high pulse width 5 ns latency-1 clock ? t wr write recovery time 0 ? ns t wlrl we# low to read latency 1 ? clock t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 119 advance information 31.3 timing diagrams 31.3.1 asynchronous re ad timing waveform mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous read cycle, clock, adv# and wait# signals are ignored. figure 31.2 timing waveform of asynchronous read cycle table 31.1 asynchronous read ac characteristics symbol speed units symbol speed units minmax minmax t rc 70 ? ns t olz 5? ns t aa ?70 t blz 5? t co ?70 t lz 10 ? t ba ?35 t chz 07 t oe ?35 t bhz 07 t oh 3? t ohz 07 data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t chz t co cs# oe# ub#, lb# address data out
120 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 31.3.1.1 page read mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous 4 page read cycle, cl ock, adv# and wait# signals are ignored. figure 31.3 timing waveform of page read cycle ta b l e 3 1 . 2 asynchronous page read ac characteristics symbol speed units symbol speed units minmax minmax t rc 70 ? ns t oh 3? ns t aa ?70 t olz 5? t pc 25 ? t blz 5? t pa ?20 t lz 10 ? t co ?70 t chz 07 t ba ?35 t bhz 07 t oe ?35 t ohz 07 data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa a22~a2 a1~a0 cs# oe# t ohz t oe t co t aa data out t chz t oh t bhz t ba t olz t blz high z t lz t rc ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 121 advance information 31.3.2 asynchronous write timing waveform asynchronous write cycle - we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. 6. condition for continuous write operation over 50 times: t wp(min) =70ns. figure 31.4 timing waveform of write cycle ta b l e 3 1 . 3 asynchronous write ac characteristics note: t wp(min) = 70ns for continuous writ e operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0? ns t cw 60 ? t wr 0? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0? t wp 55 (note 1) ? t chsp 10 address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# data out high-z high- z t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw t cshp ub#, lb#
122 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 31.3.2.1 write cycle 2 mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. figure 31.5 timing waveform of write cycle(2) ta b l e 3 1 . 4 asynchronous write ac characteristics (ub# & lb# controlled) note: t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0? ns t cw 60 ? t wr 0? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0? t wp 55 (note 1) ? address data valid we# data in data out high-z high- z t wc t cw t bw t wp t dh t dw t wr t aw t as cs# ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 123 advance information 31.3.2.1 write cycle (address latch type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for word operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address la tch type write timing, t wc is same as t aw . 3. t cw is measured from the cs# going low to the end of write. 4. t bw is measured from the ub# and lb# going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 31.6 timing waveform of write cycle (address latch type) ta b l e 3 1 . 5 asynchronous write in synchronous mode ac characteristics notes: 1. address latch type, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7? ns t bw 60 ? ns t as(a) 0? t wp 55 (note 2) ? t ah(a) 7? t wlrl 1?clock t css(a) 10 ? t as 0? ns t cw 60 ? t dw 30 ? t aw 60 ? t dh 0? we# data in t bw t wp t dh t dw data valid adv# address cs# valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high- z t wlrl 14 t aw t adv ub#, lb#
124 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 31.3.3 asynchronous write timing waveform in synchronous mode 31.3.3.1 write cycle (address latch type) mrs# = v ih , oe# = v ih , wait# = high-z, ub# and lb# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for word operation. a write ends at the earliest transition when cs# goes or and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address la tch type write timing, t wc is same as t aw . 3. t cw is measured from the cs# going low to the end of write. 4. t bw is measured from the ub# and lb# going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 31.7 timing waveform of write cycle (low adv# type) ta b l e 3 1 . 6 asynchronous write in synchronous mode ac characteristics notes: 1. address latch type, ub#, lb# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7? ns t bw 60 ? ns t as(a) 0? t wp 55 ( note 2 )? ns t ah(a) 7? t wlrl 1?clock t css(a) 10 ? t as 0? ns t cw 60 ? t dw 30 ? t aw 60 ? t dh 0? we# data in t bw t wp t dh t dw data valid adv# address cs# valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high-z t wlrl 14 t aw t adv ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 125 advance information 31.3.4 asynchronous write timing waveform in synchronous mode 31.3.4.1 write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition wh en cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 31.8 timing waveform of write cycle (low adv# type) ta b l e 3 1 . 7 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type, we# controlled. 2. twp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1?clock t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high- z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl ub#, lb#
126 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 31.3.4.2 write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition wh en cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 31.9 timing waveform of write cycle (low adv# type) ta b l e 3 1 . 8 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, ub#, lb# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1?clock t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high- z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 127 advance information 31.3.4.3 multiple write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition wh en cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. clock input does not have any affect on the asynchronous multiple write operation if t whp is shorter than the (read latency - 1) clock duration. 6. t wp(min) = 70ns for continuous write operation over 50 times. figure 31.10 timing waveform of multiple write cycle (low adv# type) ta b l e 3 1 . 9 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t whp 5ns latency-1 clock ? t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw 14 ub#, lb#
128 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 32 ac operating conditions 32.1 test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 32.1 ): cl = 30pf ? figure 32.1 ac output load circuit 50 ? dout 30pf z0= 50 ? vtt = 0.5 x v ddq
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 129 advance information 32.2 synchronous ac characteristics note: (v cc = 1.7~2.0v, t a =-40 to 85 c, maximum main clock frequency = 66mhz. parameter list symbol speed units min max burst operation (common) clock cycle time t 15 200 ns burst cycle time t bc ? 2500 address set-up time to adv# falling (burst) t as(b) 0? address hold time from adv# rising (burst) t ah(b) 7? adv# setup time t advs 5? adv# hold time t advh 7? cs# setup time to clock rising (burst) t css(b) 5? burst end to new adv# falling t beadv 7? burst stop to new adv# falling t bsadv 12 ? cs# low hold time from clock t cslh 7? cs# high pulse width t cshp 5? adv# high pulse width t adhp 5? chip select to wait# low t wl ?10 adv# falling to wait# low t awl ?10 clock to wait# high t wh ?12 chip de-select to wait# high-z t wz ?7 burst read operation ub#, lb# enable to end of latency clock t bel 1?clock output enable to end of latency clock t oel 1?clock ub#, lb# valid to low-z output t blz 5? ns output enable to low-z output t olz 5? latency clock rising ed ge to data output t cd ?10 output hold t oh 3? burst end clock to output high-z t hz ?10 chip de-select to output high-z t chz ?7 output disable to output high-z t ohz ?7 ub#, lb# disable to output high-z t bhz ?7 burst write operation we# set-up time to command clock t wes 5? ns we# hold time from command clock t weh 5? we# high pulse width t whp 5? ub#, lb# set-up time to clock t bs 5? ub#, lb# hold time from clock t bh 5? byte masking set-up time to clock t bms 7? byte masking hold time from clock t bmh 7? data set-up time to clock t ds 5? data hold time from clock t dhc 3?
130 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 32.3 timing diagrams 32.3.1 synchronous burst operation timing waveform latency = 5, burst length = 4 (mrs# = v ih ) figure 32.2 timing waveform of basic burst operation table 32.1 burst operation ac characteristics symbol speed units symbol speed units min max min max t 15 200 ns t as(b) 0? ns t bc ? 2500 t ah(b) 7? t advs 5? t css(b) 5? t advh 7? t beadv 7? 123456789101112131415 adv# address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 data in d0 d1 d3 d0 d2 t beadv burst write end clock cs# t css(b) t bc undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 131 advance information 32.3.2 synchronous burst read timing waveforms 32.3.2.1 read timings latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# toggling cons ecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 32.3 timing waveform of burst read cycle (1) ta b l e 3 2 . 2 burst read ac characteristics symbol speed units symbol speed units minmax minmax t cshp 5? ns t ohz ?7 ns t bel 1? clock t bhz ?7 t oel 1? t cd ?10 t blz 5? ns t oh 3? t olz 5? t wl ?10 t hz ?10 t wh ?12 t chz ?7 t wz ?7 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t beadv t bc lb#, ub# undefined
132 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# low holding consecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the consecutive multiple burst read op eration with holding cs# lo w is possible only throug h issuing a new adv# and address. 5. burst cycle time (t bc ) should not be over 2.5s. figure 32.4 timing waveform of burst read cycle (2) ta b l e 3 2 . 3 burst read ac characteristics symbol speed units symbol speed units minmax minmax t bel 1? clock t cd ?10 ns t oel 1? t oh 3? t blz 5? ns t wl ?10 t olz 5? t awl ?10 t hz ?10 t wh ?12 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh t beadv t bc lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 133 advance information latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). last data sustaining notes: 1. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. burst cycle time (t bc ) should not be over 2.5s. figure 32.5 timing waveform of burst read cycle (3) ta b l e 3 2 . 4 burst read ac characteristics symbol speed units symbol speed units min max min max t bel 1? clock t cd ?10 ns t oel 1? t oh 3? t blz 5? ns t wl ?10 t olz 5? t wh ?12 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t c are dq3 1234567891011121314 t bel t oel t blz t olz wait# high-z 0 t wl t wh t bc lb#, ub# undefined
134 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 32.3.2.1 write timings latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# toggling consec utive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. burst cycle time (t bc ) should not be over 2.5s. figure 32.6 timing waveform of burst write cycle (1) ta b l e 3 2 . 5 burst write ac characteristics symbol speed units symbol speed units min max min max t cshp 5? ns t whp 5? ns t bs 5? t ds 5? t bh 5? t dhc 3? t bms 7? t wl ?10 t bmh 7? t wh ?12 t wes 5? t wz ?7 t weh 5? 12345678910111213 adv# address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh t beadv t bc lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 135 advance information latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# low holding consecutive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. the consecutive multiple burst read op eration with holding cs# lo w is possible only throug h issuing a new adv# and address. 6. burst cycle time (t bc ) should not be over 2.5s. figure 32.7 timing waveform of burst write cycle (2) ta b l e 3 2 . 6 burst write ac characteristics symbol speed units symbol speed units min max min max t bs 5? ns t whp 5? ns t bh 5? t ds 5? t bms 7? t dhc 3? t bmh 7? t wl ?10 t wes 5? t awl ?10 t weh 5? t wh ?12 12345678910111213 adv address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t awl latency 5 valid valid t wh t beadv t bc lb#, ub#
136 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 32.3.3 synchronous burst read stop timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. figure 32.8 timing waveform of burst read stop by cs# ta b l e 3 2 . 7 burst read stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 ? ns t cd ?10 ns t cslh 7? t oh 3? t cshp 5? t chz ?7 t bel 1? clock t wl ?10 t oel 1? t wh ?12 t blz 5? ns t wz ?7 t olz 5? 1234567891011121314 adv# address cs# data oe# clk dq0 t cd don?t c are valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz wait# t bel t oel t blz t olz t cslh t cshp high-z 0 high- z t wl t wh t wz t wl dq1 t bsadv lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 137 advance information 32.3.4 synchronous burst write stop timing waveform latency = 5, burst length = 4, wp = low enable (oe#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. figure 32.9 timing waveform of burst write stop by cs# ta b l e 3 2 . 8 burst write stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 ? ns t whp 5? ns t cslh 7? t ds 5? t cshp 5? t dhc 3? t bs 5? t wl ?10 t bh 5? t wh ?12 t wes 5? t wz ?7 t weh 5? 12345678910111213 adv# address cs# data in we# clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t ca re t whp t bsadv t bs t bh lb#, ub#
138 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 32.3.5 synchronous burst read suspend timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. if the clock input is halted during bu rst read operation, the data output is su spended. during the burst read suspend period, oe# high drives data output to high-z. if the cloc k input is resumed, the susp ended data is output first. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. during the suspend period, oe# high drives dq to high-z and oe# low drives dq to low-z. if oe# stays low during suspend period, the previous data is sustained. 4. burst cycle time (t bc ) should not be over 2.5s. figure 32.10 timing waveform of burst read suspend cycle (1) ta b l e 3 2 . 9 burst read suspend ac characteristics symbol speed units symbol speed units min max min max t bel 1? clock t hz ?10 ns t oel 1? t ohz ?7 t blz 5? ns t wl ?10 t olz 5? t wh ?12 t cd ?10 t wz ?7 t oh 3? 123456 7891 011 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc t oh lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 139 advance information 33 transition timing waveform between read and write latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.1 synchronous burst read to asynchronous write (address latch type) table 33.1 burst read to asynchronous wr ite (address latch type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 2 1 dq1 dq3 dq2 we# t css(a) data in t dh t dw data valid high- z high-z t as(a) t ah(a) t beadv t as read laten cy 5 0 t wp t wlrl t cw t aw t bw t bc wait# high-z t wh t wl t wz high-z t adv lb#, ub#
140 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.2 synchronous burst read to asynchronous write (low adv# type) ta b l e 3 3 . 2 burst read to asynchronous write (low adv# type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t ca re t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we# data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw t as t wr valid addr ess read late ncy 5 t wlrl wait# high-z t wh t wl t wz dq3 t bc high-z lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 141 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.3 asynchronous write (address latch type) to synchronous burst read timing ta b l e 3 3 . 3 asynchronous write (address latch type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1?clock 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t wp t bw t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw t adv t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
142 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.4 asynchronous write (low adv# type) to synchronous burst read timing ta b l e 3 3 . 4 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1?clock t adhp 5? ns 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp read latency 5 t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 143 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.5 synchronous burst read to synchronous burst write timing ta b l e 3 3 . 5 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7? ns high- z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we# t css(b) data in high- z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait# t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh lb#, ub#
144 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 33.6 synchronous burst write to synchronous burst read timing ta b l e 3 3 . 6 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7? ns high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we# t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait# t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh d3 d0 dq0 dq1 dq3 dq2 high- z lb#, ub#
publication number s71ws-n_01 revision a amendment 4 issue date september 15, 2005 advance information 1.8v psram type 4 8m x 16-bit synchronous burst psram features ? process technology: cmos ? organization: 8m x16 bit power supply voltage: 1.7?2.0v ? three state outputs ? supports mrs (mode register set) ? mrs control - mrs pin control ? supports power saving modes - partial array refresh mode internal tcsr ? supports driver strength optimization for system environment power saving ? supports asynchronous 4-page read and asynchronous write operation ? supports synchronous burst read and asynchro nous write operation (address latch type and low adv type) ? supports synchronous burst read and synchronous burst write operation ? synchronous burst (read/write) operation ? supports 4 word / 8 word / 16 word and full page(256 word) burst ? supports linear burst type & interleave burst type ? latency support: latency 5 @ 66mhz(tcd 10ns) latency 4 @ 54mhz(tcd 10ns) ? supports burst read suspend in no clock toggling ? supports burst write data masking by /ub & /lb pin control ? supports wait pin function for indicating data availability. ? max. burst clock frequency: 66mhz
146 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 34 pin description 35 power up sequence after applying v cc up to minimum operating voltage (1.7v) , drive cs# high first and then drive mrs# high. this gets the device into power up mode. wait 200 s minimum to get into the normal operation mode. during power up mode, the standby current cannot be guaranteed. to obtain stable standby current levels, at least one cycle of active operation should be implemented re- gardless of wait time duration. to obtain approp riate device operation, be sure to follow the proper power up sequence. 1. apply power. 2. maintain stable power (v cc min.=1.7v) for a minimum 200 s with cs# and mrs# high. pin name function type description clk clock input commands are referenced to clk adv# address valid valid address is latched by adv falling edge mrs# mode register set mrs# low enables mode register to be set cs# chip select cs# low enables the chip to be active cs# high disables the chip and puts it into standby mode oe# output enable oe# low enables the chip to output the data we# write enable we# low enables the chip to start writing the data lb# lower byte (i/o 0 ? 7 ) ub# (lb#) low enables upper byte (lower byte) to start operating ub# upper byte (i/o 8 ? 15 ) a0-a22 address 0 ? address 22 valid addresses input when adv is low mode setting input when mrs is low i/o0-i/o15 data inputs / outputs input/output depending on ub# or lb# status, word (16-bit, ub#, and lb# low) data, upper byte (8-bit, ub# low & lb# high) data or lower byte (8-bit, lb# low, and ub# high) data is loaded v cc voltage source power core power supply v ccq voltage source power i/o power supply v ss ground source gnd core ground source v ssq i/o ground source gnd i/o ground source wait# valid data indicator output wait# in dicates whether data is valid or not
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 147 advance information 36 power up and standby mode timing diagrams 36.1 power up note: after v cc reaches v cc (min.), wait 200 s with cs# and mrs# high. this puts the device into normal operation. figure 36.1 power up timing 36.2 standby mode figure 36.2 standby mode state machines the default mode after power up is asynchronous mode (4 page read and asynchronous write). but this default mode is not 100% guaranteed, so the mrs# setting sequence is highly recom- mended after power up. for entry to par mode, drive the mrs# pin into v il for over 0.5s or longer (suspend period) during standby mode after the mrs# setting has been completed (a4=1, a3=0). if the mrs# pin is driven into v ih during par mode, the device reverts to standby mode without the wake up sequence. ~ ~ v cc v cc(min) min. mrs# cs# min. 0ns power up mode min. 0ns normal operation 200 s 200 s ~ ~ ~ ~ active standby mode par mode mrs setting cs# = v ih mrs# = v ih cs# = ub# = lb# = v il we# = v il , mrs# = v il cs# = v il , ub# or lb# = v il mrs# = v ih cs# = v ih mrs# = v ih mrs# = v il cs# = v il we# = v il , mrs#=v il mrs setting initial state (wait 200s) power on
148 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 37 functional description table 37.1 asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) legend: x = don?t care (must be low or high state). notes: 1. in asynchronous mode, clock and adv# are ignored. 2. the wait# pin is high-z in asynchronous mode. ta b l e 3 7 . 2 synchronous burst read & asynchronous write mode (a15/a14=0/1) notes: 1. x must be low or high state. 2. x means ?don?t care? (can be low, high or toggling). 3. wait# is the device output signal and does not have any a ffect on the mode definition. pl ease refer to each timing diagram for wait# pin function. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 power deselected h h x x x x high-z high-z standby deselected h l x x x x high-z high-z par output disabled l h h h x x high-z high-z active outputs disabled l h x x h h high-z high-z active lower byte read l h l h l h d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l h h l l h d in high-z active upper byte write l h h l h l high-z d in active word write l h h l l l d in d in active mode register set l l h l l l high-z high-z active mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x x x x high-z high-z x (note 2) x (note 2) standby deselected h l x x x x high-z high-z x (note 2) x (note 2) par output disabled l h h h x x high-z high-z x (note 2) hactive outputs disabled l h x x h h high-z high-z x (note 2) hactive read command l h x h x x high-z high-z active lower byte read l h l h l h d out high-z h active upper byte read l h l h h l high-z d out hactive word read l h l h l l d out d out hactive lower byte write l h h l l h d in high-z x (note 2) active upper byte write l h h l h l high-z d in x (note 2) active word write l h h l l l d in d in x (note 2) active mode register set l l h l l l high-z high-z x (note 2) active or or or or
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 149 advance information ta b l e 3 7 . 3 synchronous burst read & synchronous burst write mode(a15/a14 = 1/0) notes: 1. x must be low or high state. 2. x means ?don?t care? (can be low, high or toggling). 3. wait# is the device output signal and does not have any a ffect on the mode definition. pl ease refer to each timing diagram for wait# pin function. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x (note1) x (note1) x (note1) x (note1) high-z high-z x (note 2) x (note 2) standby deselected h l x (note1) x (note1) x (note1) x (note1) high-z high-z x (note 2) x (note 2) par output disabled l h h h x x high-z high-z x (note 2) hactive outputs disabled lh x (note1) x (note1) h h high-z high-z x (note 2) hactive read command l h x (note1) h x x high-z high-z active lower byte read lh l h l h d out high-z h active upper byte read lh l h h lhigh-zd out hactive word read l h l h l l d out d out hactive write command l h x (note1) high-z high-z active lower byte write lh h x (note1) lhd in high-z h active upper byte write lh h x (note1) hlhigh-zd in hactive word write l h h x (note1) lld in d in hactive mode register set l l h l l high-z high-z active or l or l
150 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 38 mode register setting operation the device has several modes: ? asynchronous page read mode ? asynchronous write mode ? synchronous burst read mode ? synchronous burst write mode ? standby mode and partial array refresh (par) mode. partial array refresh (par) mode is defined through the mode register set (mrs) option. the mrs option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode. 38.1 mode register set (mrs) the mode register stores the data for controllin g the various operation modes of the psram. it programs partial array refresh (par), burst length, burst type, latency count and various vendor specific options to make psram useful for a variety of different applications. the default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. the mode register is written by driving cs#, adv#, we#, ub#, lb# and mrs# to v il and driving oe# to v ih during valid addressing. the mode register is divided into various fields depending on the fields of functions. the par field uses a0?a4, burst length field uses a5?a7, burst type uses a8, latency count uses a9?a11, wait polarity uses a13, operation mode uses a14?a15 and driver strength uses a16?a17. refer to the table below for detailed mode regist er settings. a18?a22 addresses are ?don?t care? in the mode register setting. table 38.1 mode register setting according to field of function note: ds (driver strength), ms (mod e select), wp (wait polarity), latency (latency count), bt (burst type), bl (burst length), par (partial array refresh), para (partial array refresh array), pars (par tial array refresh size), rfu (reserved for future use). ta b l e 3 8 . 2 mode register set address a17 ? a16 a15 ? a14 a13 a12 a11 ? a19 a8 a7 ? a5 a4 ? a3 a2 a1 ? a0 function ds ms wp rfu latency bt bl par para pars driver strength mode select a17 a16 ds a15 a14 ms 0 0 full drive (note 1) 0 0 async. 4 page read / async. write (note 1) 0 1 1/2 drive 0 1 sync. burst read / async. write 1 0 1/4 drive 1 0 sync. burst read / sync. burst write wait# polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl 0low enable (note 1)0 must (note 1) 0 0 0 3 0 linear (note 1) 0 1 0 4 word 1 high enable 1 ? 0 0 1 4 1 interleave 0 1 1 8 word 0 1 0 5 1 0 0 16 word (note 1) 0 1 1 6 1 1 1 full (256 word)
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 151 advance information note: default mode. the address bits other th an those listed in the table above ar e reserved. for example, burst length address bits(a7:a6:a5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. if the reserved address bits are input, then the mode will be set to the default mode. each field ha s its own default mode, but this default mode is not 100% guar - anteed, so the mrs setting sequence is highly recommended af ter power up. a12 is a reserved bit for future use. a12 must be set as ?0?. not all the mode settings are tested. per the mode settings to be tested, please contact spansion. the 256 word full page burst mode needs to meet t bc (burst cycle time) parameter as max. 2500ns. 38.2 mrs pin control type mo de register setting timing in this device, the mrs pin is used for two purposes. one is to get into the mode register setting and the other is to execute partial array refresh mode. to get into the mode register setting, the system must drive the mrs# pin to v il and immediately (within 0.5s) issue a write command (dri ve cs#, adv#, ub#, lb# and we# to v il and drive oe# to v ih during valid address). if the subsequent write command (we# signal input) is not issued within 0.5s, then the device may get into the par mode. figure 38.1 mode register setting timing (oe# = v ih ) ta b l e 3 8 . 3 mrs ac characteristics note: v cc =1.7 ? 2.0v, t a =-40 to 85c, maximum main clock frequency=66mhz partial array refresh par array par size a4 a3 par a2 para a1 a0 pars 1 0 par enable 0 bottom array (note 1) 0 0 full array (note 1) 1 1 par disable (note 1) 1 top array 0 1 3/4 array 1 0 1/2 array 1 1 1/4 array parameter list symbol speed units min max mrs mrs# enable to register write start t mw 0 500 ns end of write to mrs# disable t wu 0 ? ns t wu address we# t wc t cw t aw t bw t wp t as cs# t mw adv# mrs# 12345678910111213 clk 0 (mrs setting timing) 1. clock input is ignored. ub#, lb# register write start register write complete register update complete
152 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 39 asynchronous operation 39.1 asynchronous 4 page read operation asynchronous normal read operation starts wh en cs#, oe# and ub# or lb# are driven to v il under the valid address without toggling page addr esses (a0, a1). if the page addresses (a0, a1) are toggled under the other valid address, the firs t data will be out with the normal read cycle time (trc) and the second, the third and the fourth data will be out with the page cycle time (tpc). (mrs# and we# should be driven to v ih during the asynchronous (page) read operation) clock, adv#, wait# signals are ignored during th e asynchronous (page) read operation. 39.2 asynchronous write operation asynchronous write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid address. mrs# and oe# should be driven to v ih during the asynchronous write operation. clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. 39.3 asynchronous write oper ation in synchronous mode a write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid ad- dress. clock input does not have any affect to the write operation (mrs# and oe# should be driven to v ih during write operation. adv# can be either toggling for address latch or held in v il ). clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. figure 39.1 asynchronous 4-page read figure 39.2 asynchronous write a1~a0 cs# oe# a22~a2 ub#, lb# data out high-z high- z high-z address cs# we# data in data out ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 153 advance information 40 synchronous burst operation burst mode operations enable the system to get high performance read and write operation. the address to be accessed is latched on the rising edge of clock or adv# (whichever occurs first). cs# should be setup before the address latch. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# high) or a write (we# low). for the optimized burst mode of each system, the system should determine how many clock cy- cles are required for the first data of each burst access (latency count), how many words the device outputs during an access (burst length) and which type of burst operation (burst type: linear or interleave) is needed. the wait polarity should also be determined (see ta b l e 3 8 . 2 ). 40.1 synchronous burst read operation the synchronous burst read command is implemented when the clock rising is detected during the adv# low pulse. adv# and cs# should be se t up before the clock rising. during the read command, we# should be held in v ih . the multiple clock risings (during the low adv# period) are allowed, but the burst operation starts from the first clock rising. the first data will be out with latency count and t cd . 40.2 synchronous burst write operation the synchronous burst write command is implemented when the clock rising is detected during the adv# and we# low pulse. adv#, we# and cs# should be set up before the clock rising. the multiple clock risings (during the low adv# peri od) are allowed but, the burst operation starts from the first clock rising. the first data w ill be written in the latency clock with t ds . note: latency 5, bl 4, wp: low enable figure 40.1 synchronous burst read note: latency 5, bl 4, wp: low enable figure 40.2 synchronous burst write clk adv# addr. oe# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ub#, lb# wait# data out clk adv# addr . we# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 wait# data in ub#, lb#
154 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 41 synchronous burst operation terminology 41.1 clock (clk) the clock input is used as the reference for sy nchronous burst read and write operation of the psram. the synchronous burst read and write operat ions are synchronized to the rising edge of the clock. the clock transitions must swing between v il and v ih . 41.2 latency count the latency count configuration tells the device how many clocks must elapse from the burst command before the first data should be availabl e on its data pins. this value depends on the input clock frequency. ta b l e 4 1 . 1 shows the supported latency count. table 41.1 latency count support ta b l e 4 1 . 2 number of clocks for 1st data note: the first data will always keep the latency. from the second data on, some period of wait time may be caused by wait# pin. figure 41.1 latency configuration (read) 41.3 burst length burst length identifies how many data the device outputs during an access. the device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word full page burst mode needs to meet t bc (burst cycle time) pa rameter as 2500ns max. the first data will be output with the set latency + t cd . from the second data on, the data will be output with t cd from each clock. clock frequency up to 66 mhz up to 54 mhz up to 40 mhz latency count 543 set latency latency 3 latency 4 latency 5 # of clocks for 1st data (read) 456 # of clocks for 1st data (write) 234 address data out adv# clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 155 advance information 41.4 burst stop burst stop is used when the system wants to stop burst operation on purpose. if driving cs# to v ih during the burst read operation, the burst oper ation is stopped. during the burst read oper- ation, the new burst operation cannot be issued. the new burst operation ca n be issued only after the previous burst operation is finished. the burst stop feature is very us eful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst, used mostly in the mobile handset application environment. 41.5 wait control (wait#) the wait# signal is the device?s output signal that indicates to the host system when it?s data- out or data-in is valid. to be compatible with the flash interfaces of various microprocessor types, the wait# polarity (wp) can be configured. the polarity can be programmed to be either low enable or high enable. for the timing of wait# signal, the wait# signal sh ould be set active one clock prior to the data regardless of read or write cycle. note: latency: 5, burst length: 4, wp: low enable figure 41.2 wait# and read/write latency control 12345678910111213 adv# read clk dq0 dq1 0 dq2 write d0 d1 d2 dq3 d3 data out data in cs# latency 5 latency 5 high-z wait# high-z wait#
156 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 41.6 burst type the device supports linear type burst sequence and interleave type burst sequence. linear type burst sequentially increments the burst address from the starting address. the detailed linear and interleave type burst address sequence is shown in ta b l e 4 1 . 3 . ta b l e 4 1 . 3 burst sequence start address burst address sequence (decimal) wrap (note 1) 4 word burst 8 word burst 16 word burst full page(256 word) linear interleave linear interleave linear interleave linear 0 0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1 -2-...-14-15 0-1-2-3-4...14-15 0-1-2-...-254-255 1 1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6 1 -2-3-...-15-0 1-0-3-2-5...15-14 1-2-3-...-255-0 2 2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5 2-3-4-...-0-1 2-3-0-1-6...12-13 2-3-4-...-255-0-1 3 3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4 3-4-5-...-1-2 3-2-1-0-7...13-12 3-4-5-...-255-0-1-2 4 4-5-...-1-2-3 4-5-6-...-2-3 4-5-6-...-2-3 4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3 5 5-6-...-2-3-4 5-4-7-...-3-2 5-6-7-...-3 -4 5-4-7-6-1...11-10 5-6-7-...-255-...-3-4 6 6-7-...-3-4-5 6-7-4-...-0-1 6-7-8-...-4-5 6-7-4-5-2...8-9 6-7-8-...-255-...-4-5 7 7-0-...-4-5-6 7-6-5-...-1-0 7-8-9-...-5-6 7-6-5-4-3...9-8 7-8-9-...-255-...-5-6 ???? 14 14-15-0-...-12-13 14-15-12-...-0-1 14-15-...-255-...-12-13 15 15-0-1-...-13-14 15-14-13-...-1-0 15-16-...-255-...-13-14 ? ? 255 255-0-1-...-253-254
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 157 advance information 42 low power features 42.1 internal tcsr the internal temperature compensated self refresh (tcsr) feature is a very useful tool for re- ducing standby current at room temperature (b elow 40c). dram cells have weak refresh characteristics in higher temperatures. high temp eratures require more refresh cycles, which can lead to standby current increase. without the internal tcsr, the refresh cycle should be set at worst condition so as to cover the high temperature (85c) refresh characteristics. but with internal tcsr, a refresh cycle below 40c can be optimized, so the standby current at room temperature can be greatly reduced. this feature is beneficial si nce most mobile phones are used at or below 40c in the phone standby mode. figure 42.1 par mode execution and exit table 42.1 par mode characteristics notes: 1. only the data in the refreshed block are valid. 2. the par array can be selected through mode register set (see mode register setting operation ). 42.2 driver strength optimization the optimization of output driver strength is po ssible through the mode register setting to adjust for the different data loadings. through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. the device supports full drive, 1/2 drive and 1/4 drive. 42.3 partial array refresh (par) mode the par mode enables the user to specify the active memory array size. the psram consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays through the mode register setting. the active memory array is periodically refreshed whereas the disabled array is not refreshe d, so the previously stored data is lost. even though par mode is enabled through the mode register setting, par mode execution by the mrs# pin is still needed. the normal operation can be executed ev en in refresh-disabled array as long as the mrs# pin is not driven to the low condition for over 0.5s. driving the mrs# pin to the high condition puts the device back to the normal operation mode from the par executed mode. refer to figure 42.1 and ta b l e 4 2 . 1 for par operation and par address mapping. power mode address (bottom array) (note 2) address (top array) (note 2) memory cell data standby current (a, max) wait time (s) standby (full array) 000000h ? 7fffffh 000000h ? 7fffffh valid (note 1) 200 0 partial refresh(3/4 block) 000000h ? 5fffffh 200000h ? 7fffffh 170 partial refresh(1/2 block) 000000h ? 3fffffh 400000h ? 7fffffh 150 partial refresh(1/4 block) 000000h ? 1fffffh 600000h ? 7fffffh 140 mrs# mode cs# normal operation 0.5 s suspend par mode normal operation
158 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 43 absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. functional operation should be restricted to use under recommended operating conditions only. exposure to absolute maxi - mum rating conditions longer than one second may a ffect reliability. 44 dc recommended operating conditions notes: 1. ta=-40 to 85c, unle ss otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. 45 capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled period ically and is not 100% tested. item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc +0.3v v power supply voltage relative to v ss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c symbol parameter min typ max unit v cc power supply voltage 1.7 1.85 2.0 v v ss ground 0 0 0 v ih input high voltage 0.8 x v cc ?v cc + 0.2 (note 2) v il input low voltage -0.2 (note 3) ?0.4 symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c io input/output capacitance v out = 0v ? 10 pf
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 159 advance information 46 dc and operating characteristics 46.1 common notes: 1. full array partial refresh current (i sbp ) is same as standby current (i sb1 ). 47 ac operating conditions 47.1 test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 47.1 ): cl=50pf figure 47.1 par mode execution and exit item symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs#=v ih , mrs#=v ih , oe#=v ih or we#=v il , v io =v ss to v cc -1 ? 1 a average operating current i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs#=v il , mrs#=v ih , v in =v il or v ih ? ? 40 ma output low voltage v ol i ol =0.1ma ? ? 0.2 v output high voltage v oh i oh =-0.1ma 1.4 ? ? v standby current (cmos) i sb1 cs# v cc -0.2v, mrs# v cc -0.2v, other inputs = v ss to v cc < 40c ? ? tbd a < 85c ? ? 200 a partial refresh current i sbp (note 1) mrs# 0.2v, cs# v cc -0.2v other inputs = v ss to v cc < 40c 3/4 block ? ? tbd a 1/2 block ? ? tbd 1/4 block ? ? tbd < 85c 3/4 block ? ? 170 a 1/2 block ? ? 150 1/4 block ? ? 140 50 dout 30pf z0= 50 vtt = 0.5 x v ddq
160 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 47.2 asynchronous ac characteristics (v cc =1.7?2.0v, t a =?40 to 85 c) note: t wp (min)=70ns for continuous write operation over 50 times. symbol parameter speed bins unit min max read t rc read cycle time 70 ? ns t pc page read cycle time 25 ? ns t aa address access time ? 70 ns t pa page access time ? 20 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 35 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 5 ? ns t olz output enable to low-z output 5 ? ns t chz chip disable to high-z output 0 7 ns t bhz ub#, lb# disable to high-z output 0 7 ns t ohz output disable to high-z output 0 7 ns t oh output hold 3 ? ns write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t adv adv# minimum low pulse width 7 ? ns t as address set-up time to beginning of write 0 ? ns t as(a) address set-up time to adv# falling 0 ? ns t ah(a) address hold time from adv# rising 7 ? ns t css(a) cs# setup time to adv# rising 10 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 (note 1) ? ns t whp we# high pulse width 5 ns latency-1 clock ? t wr write recovery time 0 ? ns t wlrl we# low to read latency 1 ? clock t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 161 advance information 47.3 timing diagrams 47.3.1 asynchronous re ad timing waveform mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous read cycle, clock, adv# and wait# signals are ignored. figure 47.2 timing waveform of asynchronous read cycle table 47.1 asynchronous read ac characteristics symbol speed units symbol speed units minmax minmax t rc 70 ? ns t olz 5? ns t aa ?70 t blz 5? t co ?70 t lz 10 ? t ba ?35 t chz 07 t oe ?35 t bhz 07 t oh 3? t ohz 07 data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t chz t co cs# oe# ub#, lb# address data out
162 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 47.3.1.1 page read mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous 4 page read cycle, cl ock, adv# and wait# signals are ignored. figure 47.3 timing waveform of page read cycle ta b l e 4 7 . 2 asynchronous page read ac characteristics symbol speed units symbol speed units minmax minmax t rc 70 ? ns t oh 3? ns t aa ?70 t olz 5? t pc 25 ? t blz 5? t pa ?20 t lz 10 ? t co ?70 t chz 07 t ba ?35 t bhz 07 t oe ?35 t ohz 07 data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa a22~a2 a1~a0 cs# oe# t ohz t oe t co t aa data out t chz t oh t bhz t ba t olz t blz high z t lz t rc ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 163 advance information 47.3.2 asynchronous write timing waveform asynchronous write cycle - we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. figure 47.4 timing waveform of write cycle ta b l e 4 7 . 3 asynchronous write ac characteristics note: t wp(min) = 70ns for continuous writ e operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0? ns t cw 60 ? t wr 0? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0? t wp 55 (note 1) ? address we# d ata i n t wc t cw t aw t bw t wp t as t dh t dw high-z high-z data valid cs# t wr data out high- z high-z ub#, lb#
164 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 47.3.2.1 write cycle 2 mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. figure 47.5 timing waveform of write cycle(2) ta b l e 4 7 . 4 asynchronous write ac characteristics (ub# & lb# controlled) note: t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0? ns t cw 60 ? t wr 0? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0? t wp 55 (note 1) ? address data valid we# data in data out high-z high- z t wc t cw t bw t wp t dh t dw t wr t aw t as cs# ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 165 advance information 47.3.2.1 write cycle (address latch type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for word operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address la tch type write timing, t wc is same as t aw . 3. t cw is measured from the cs# going low to the end of write. 4. t bw is measured from the ub# and lb# going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 47.6 timing waveform of write cycle (address latch type) ta b l e 4 7 . 5 asynchronous write in synchronous mode ac characteristics notes: 1. address latch type, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7? ns t bw 60 ? ns t as(a) 0? t wp 55 (note 2) ? t ah(a) 7? t wlrl 1?clock t css(a) 10 ? t as 0? ns t cw 60 ? t dw 30 ? t aw 60 ? t dh 0? we# data in t bw t wp t dh t dw data valid adv# address cs# valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high- z t wlrl 14 t aw t adv ub#, lb#
166 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 47.3.1 asynchronous write timing waveform in synchronous mode 47.3.1.1 write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. low adv# type write cycle - we# controlled. 2. a write occurs during the overlap (twp) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 47.7 timing waveform of write cycle (low adv# type) ta b l e 4 7 . 6 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type, we# controlled. 2. twp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1?clock t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high- z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 167 advance information 47.3.1.2 write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. low adv# type write cycl e - ub# and lb# controlled. 2. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect to the write operation if the parameter t wlrl is met. figure 47.8 timing waveform of write cycle (low adv# type) ta b l e 4 7 . 7 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, ub#, lb# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1?clock t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high- z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z ub#, lb#
168 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 47.3.1.3 multiple write cycle (low adv# type) mrse = v ih , oe# = v ih , wait# = high-z, we# controlled\ notes: 1. low adv# type multiple write cycle. 2. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begi ns when cs# goes low and we# goes low with asserting ub# or lb# for sing le byte operation or simultaneously asserting ub# and lb # for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect on the asynchronous multiple write operation if t whp is shorter than the (read latency - 1) clock duration. 7. t wp(min) = 70ns for continuous write operation over 50 times. figure 47.9 timing waveform of multiple write cycle (low adv# type) ta b l e 4 7 . 8 asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t whp 5ns latency-1 clock ? t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw 14 ub#, lb#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 169 advance information 48 ac operating conditions 48.1 test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 48.1 ): cl = 30pf ? figure 48.1 ac output load circuit 50 ? dout 30pf z0= 50 ? vtt = 0.5 x v ddq
170 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 48.2 synchronous ac characteristics note: 3.(v cc = 1.7 ? 2.0v, ta=-40 to 85 c, maximum main clock frequency = 66mhz. 48.3 timing diagrams 48.3.1 synchronous burst operation timing waveform latency = 5, burst length = 4 (mrs# = v ih ) parameter list symbol speed units min max burst operation (common) clock cycle time t 15 200 ns burst cycle time t bc ? 2500 address set-up time to adv# falling (burst) t as(b) 0? address hold time from adv# rising (burst) t ah(b) 7? adv# setup time t advs 5? adv# hold time t advh 7? cs# setup time to clock rising (burst) t css(b) 5? burst end to new adv# falling t beadv 7? burst stop to new adv# falling t bsadv 12 ? cs# low hold time from clock t cslh 7? cs# high pulse width t cshp 55 ? adv# high pulse width t adhp ?? chip select to wait# low t wl ?10 adv# falling to wait# low t awl ?10 clock to wait# high t wh ?12 chip de-select to wait# high-z t wz ?7 burst read operation ub#, lb# enable to end of latency clock t bel 1?clock output enable to end of latency clock t oel 1?clock ub#, lb# valid to low-z output t blz 5? ns output enable to low-z output t olz 5? latency clock rising ed ge to data output t cd ?10 output hold t oh 3? burst end clock to output high-z t hz ?10 chip de-select to output high-z t chz ?7 output disable to output high-z t ohz ?7 ub#, lb# disable to output high-z t bhz ?7 burst write operation we# set-up time to command clock t wes 5? ns we# hold time from command clock t weh 5? we# high pulse width t whp 5? ub#, lb# set-up time to clock t bs 5? ub#, lb# hold time from clock t bh 5? byte masking set-up time to clock t bms 7? byte masking hold time from clock t bmh 7? data set-up time to clock t ds 5? data hold time from clock t dhc 3?
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 171 advance information figure 48.2 timing waveform of basic burst operation table 48.1 burst operation ac characteristics symbol speed units symbol speed units min max min max t 15 200 ns t as(b) 0? ns t bc ? 2500 t ah(b) 7? t advs 5? t css(b) 5? t advh 7? t beadv 7? 123456789101112131415 adv# address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 data in d0 d1 d3 d0 d2 t beadv burst write end clock cs# t css(b) t bc undefined
172 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 48.3.2 synchronous burst read timing waveforms 48.3.2.1 read timings latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# toggling cons ecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 48.3 timing waveform of burst read cycle (1) ta b l e 4 8 . 2 burst read ac characteristics symbol speed units symbol speed units minmax minmax t cshp 5? ns t ohz ?7 ns t bel 1? clock t bhz ?7 t oel 1? t cd ?10 t blz 5? ns t oh 3? t olz 5? t wl ?10 t hz ?10 t wh ?12 t chz ?7 t wz ?7 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t beadv t bc lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 173 advance information latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# low holding consecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the consecutive multiple burst read op eration with holding cs# lo w is possible only throug h issuing a new adv# and address. 5. burst cycle time (t bc ) should not be over 2.5s. figure 48.4 timing waveform of burst read cycle (2) ta b l e 4 8 . 3 burst read ac characteristics symbol speed units symbol speed units minmax minmax t bel 1? clock t cd ?10 ns t oel 1? t oh 3? t blz 5? ns t wl ?10 t olz 5? t awl ?10 t hz ?10 t wh ?12 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh t beadv t bc lb#, ub# undefined
174 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). last data sustaining notes: 1. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. burst cycle time (t bc ) should not be over 2.5s. figure 48.5 timing waveform of burst read cycle (3) ta b l e 4 8 . 4 burst read ac characteristics symbol speed units symbol speed units min max min max t bel 1? clock t cd ?10 ns t oel 1? t oh 3? t blz 5? ns t wl ?10 t olz 5? t awl ?12 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t c are dq3 1234567891011121314 t bel t oel t blz t olz wait# high-z 0 t wl t wh t bc lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 175 advance information 48.3.2.1 write timings latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# toggling consec utive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. burst cycle time (t bc ) should not be over 2.5s. figure 48.6 timing waveform of burst write cycle (1) ta b l e 4 8 . 5 burst write ac characteristics symbol speed units symbol speed units minmax minmax t cshp 5? ns t whp 5? ns t bs 5? t ds 5? t bh 5? t dhc 3? t bms 7? t wl ?10 t bmh 7? t wh ?12 t wes 5? t wz ?7 t weh 5? 12345678910111213 adv# address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh t beadv t bc lb#, ub#
176 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# low holding consecutive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. the consecutive multiple burst read op eration with holding cs# lo w is possible only throug h issuing a new adv# and address. 6. burst cycle time (t bc ) should not be over 2.5s. figure 48.7 timing waveform of burst write cycle (2) ta b l e 4 8 . 6 burst write ac characteristics symbol speed units symbol speed units min max min max t bs 5? ns t whp 5? ns t bh 5? t ds 5? t bms 7? t dhc 3? t bmh 7? t wl ?10 t wes 5? t awl ?10 t weh 5? t wh ?12 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh t beadv t bc lb#, ub# undefined
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 177 advance information 48.3.3 synchronous burst read stop timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. figure 48.8 timing waveform of burst read stop by cs# ta b l e 4 8 . 7 burst read stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 ? ns t cd ?10 ns t cslh 7? t oh 3? t cshp 5? t chz ?7 t bel 1? clock t wl ?10 t oel 1? t wh ?12 t blz 5? ns t wz ?7 t olz 5? 1234567891011121314 adv# address cs# data oe# clk dq0 t cd don?t c are valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz wait# t bel t oel t blz t olz t cslh t cshp high-z 0 high- z t wl t wh t wz t wl dq1 t bsadv lb#, ub# undefined
178 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 48.3.4 synchronous burst write stop timing waveform latency = 5, burst length = 4, wp = low enable (oe#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. figure 48.9 timing waveform of burst write stop by cs# ta b l e 4 8 . 8 burst write stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 ? ns t whp 5? ns t cslh 7? t ds 5? t cshp 5? t dhc 3? t bs 5? t wl ?10 t bh 5? t wh ?12 t wes 5? t wz ?7 t weh 5? 12345678910111213 adv# address cs# data in we# clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t ca re t whp t bsadv t bs t bh lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 179 advance information 48.3.5 synchronous burst read suspend timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. if the clock input is halted during burst read operation, the data output w ill be suspended. during the burst read suspend period, oe# high drives data ou tput to high-z. if the clock input is resumed, the suspended data will be output first. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. during the suspend period, oe# high drives dq to high-z and oe# low drives dq to low-z. if oe# stays low during suspend period, the previous data will be sustained. 4. burst cycle time (t bc ) should not be over 2.5s. figure 48.10 timing waveform of burst read suspend cycle (1) ta b l e 4 8 . 9 burst read suspend ac characteristics symbol speed units symbol speed units min max min max t bel 1? clock t hz ?10 ns t oel 1? t ohz ?7 t blz 5? ns t wl ?10 t olz 5? t wh ?12 t cd ?10 t wz ?7 t oh 3? 123456 7891 011 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc t oh lb#, ub# undefined
180 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 49 transition timing waveform between read and write latency = 5, burst length = 4, wp = low enable (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.1 synchronous burst read to asynchronous write (address latch type) table 49.1 burst read to asynchronous write (address latch type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 2 1 dq1 dq3 dq2 we# t css(a) data in t dh t dw data valid high- z high-z t as(a) t ah(a) t beadv t as read laten cy 5 0 t wp t wlrl t cw t aw t bw t bc wait# high-z t wh t wl t wz high-z t adv lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 181 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.2 synchronous burst read to asynchronous write (low adv# type) ta b l e 4 9 . 2 burst read to asynchronous write (low adv# type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t ca re t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we# data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw t as t wr valid addr ess read late ncy 5 t wlrl wait# high-z t wh t wl t wz dq3 t bc high-z lb#, ub#
182 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.3 asynchronous write (address latch type) to synchronous burst read timing ta b l e 4 9 . 3 asynchronous write (address latch type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1?clock 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t wp t bw t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw t adv t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 183 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.4 asynchronous write (low adv# type) to synchronous burst read timing ta b l e 4 9 . 4 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1?clock t adhp ?ns 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp read latency 5 t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
184 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.5 synchronous burst read to synchronous burst write timing ta b l e 4 9 . 5 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7? ns high- z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we# t css(b) data in high- z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait# t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh lb#, ub#
september 15, 2005 s71ws-n_01_a4 S71WS-NX0 based mcps 185 advance information latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period . the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 49.6 synchronous burst write to synchronous burst read timing ta b l e 4 9 . 6 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7? ns high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we# t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait# t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh d3 d0 dq0 dq1 dq3 dq2 high- z lb#, ub#
186 S71WS-NX0 based mcps s71ws-n_01_a4 september 15, 2005 advance information 50 revisions revision a (february 1, 2004) initial release revision a1 (february 9, 2005) updated document to include burst speed of 66 mhz updated publication number revision a2 (april 11, 2005) updated product selector guide and ordering information tables revision a3 (may 13, 2005) updated the entire utram module revision a4 (september 15, 2005) added 128-mb module. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reac tion control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2004-2005 spansion llc. all rights reserved. spansion , the spansion logo, and mirrorbi t are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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